Interposer-based Heterogeneous Processing for Efficient Exascale Systems

Thursday, 18 February 2016 at 14:30 in room INF 328

Wayne Burleson, AMD Research, Boston, MA and University of Massachusetts, Amherst, MA, USA

 

Abstract:

Exascale systems for high-performance computing and big data (ie supercomputers) will drive  new technologies from software and architectures, to circuits and manufacturing technologies. The US Department of Energy has set a goal of 50 GFLOPS/Watt for an Exascale system in 2023. This requires significant innovations in energy efficiency, ranging from low-voltage techniques and novel memory systems, to accelerators such as GPUs and FPGAs. (DARPA has set a similar target of 20 pJ/op for systems ranging from embedded medical devices to supercomputers). This talk reviews recently published work from AMD Research on exascale technologies, and funded by the US DOE.

After an introduction to the various layers and challenges involved, a deep dive on interposer-based technologies will be presented. Interposers provide a new technology for assembling subsystems of heterogeneous processors and make us re-think how to partition systems to maximize energy efficiency, performance and reliability, while minimizing manufacturing, test and operating costs.

The concept of "dis-integration" of large die into smaller die connected via interposer flies in the face of the conventional wisdom to integrate as much as possible.  Heterogeneity in terms of CMOS technology node as well as architectural function is shown to provide a compromise between cost, performance and efficiency while meeting exascale goals. These technologies are also being explored for future AMD products, from clients for game consoles, high-end graphics and virtual reality, to enterprise and cloud servers.
 

Wayne Burleson is Senior Fellow at AMD Research since 2012, leading research in energy-efficient circuits and systems. He is also ECE Professor at University of Massachusetts, Amherst since 1990, where he teaches and conducts research in VLSI design, security engineering and the design and application of microelectronics for power-constrained applications.

He is an IEEE Fellow for contributions to signal processing and integrated circuit design.

Prof. Burleson has interacted with the semiconductor industry extensively throughout his career and has also had three sabbaticals in Europe including  Telecom/Paris,  LIRM Montpellier and most recently, EPFL in 2010-11.