Architecting for Changing Technology Landscape

Wednesday, 26 June 2013 at 11h00 in room INF 328

Anupam Chattopadhyay, RWTH Aachen, Germany

 

Abstract:

The inevitable roadblocks in the evolution of Moore‘s law, that powered the digital revolution for last five decades, is continuously raising the question of „what is next“ to the research community. For each possibility to continue pushing Moore‘s law, it brings forward a complex multi-layered challenge starting from a stable, scalable manufacturing of the device to the design of most efficient system architecture taking advantage of the technology. In this presentation, we view the ripples of the changing technology landscape from the perspective of a high-level synthesis and system designer.

There are two general criteria used for evaluation of all post-CMOS technoloqies namely, energy-efficiency and reliability. We will discuss how we address those by enhanced tooling and architectural solutions. Energy-efficiency of a system is significantly improved for a heterogeneous multiprocessor system. In the second part of the presentation, we discuss the biggest challenges of heterogeneous system design and how we approach that via pattern-based IP design. The presentation wil be concluded with a summary of important open problems.

About the Speaker:

Anupam Chattopadhyay received his B.E. degree from Jadavpur University, India in 2000. He received his MSc. from ALaRI, Switzerland and PhD from RWTH Aachen in 2002 and 2008 respectively. During his PhD, he worked on automatic RTL generation from the architecture description language LISA, which was commercialized later by CoWare (now part of Synopsys). In his doctoral thesis, he proposed a language-based modeling, exploration and implementation framework for partially re-configurable processors. From 2008 to 2010 he spent in CoWare R&D, as a member of consulting staff. He has published more than 40 technical papers, authored one book and several book-chapters in the above research areas. Since 2010, Prof. Dr.-Ing. Chattopadhyay is heading the research group of MPSoC Architectures in RWTH Aachen, Germany.