How Emerging Transistor Technologies Impact Circuits and Non-Boolean Architectures

Wednesday, 29 October 2014 at 14:00 in INF 328

Michael T. Niemier, Department of Computer Science and Engineering, University of Notre Dame, Indiana, USA

 

Abstract:
Historically, Moore’s Law scaling was accompanied by remarkable improvements in chip-level performance.  However, in 2003, the “status quo” for device scaling became unsustainable as off-state leakage currents exacerbated chip-level power budgets.  While technological advances (high-k, FinFETs, etc.) have helped keep power budgets in check, the performance scaling trends associated with Moore’s Law have been continued in no small part due to multi-core architectures and enchanted parallelism.  Still, using transistor scaling and core scaling to continue performance scaling trends looks to be increasingly in doubt.  Recent studies suggest that (i) if core scaling continues unabated, chip power densities will approach 500 W/cm2, and (ii) even with new devices/improved voltage scaling, only the most highly parallelizable benchmarks (>99%) will achieve speedups that mirror historical trends.  To combat the aforementioned challenges, my research group (along with other collaborators at the University of Notre Dame) are studying how non-Boolean/non-von Neumann/brain-inspired computer architectures could lead to significant performance improvements for different classes of information processing tasks.  In this presentation, I will highlight how emerging transistor technologies could impact the performance and capabilities of said architectures.  “Traditional” cellular neural networks (CNNs), CNN-inspired architectures (e.g., diffusion networks), associative memories, and new circuit topologies will all be discussed in the context of tunneling transistors (i.e., TFETs) as well as Symmetric graphene-insulator-graphene FETs (i.e., SymFETs).
 

About the speaker:

Michael T. Niemier is currently an Associate Professor at the University of Notre Dame.  His research interests include designing, facilitating, and evaluating circuits and architectures based on emerging technologies.  Currently, Niemier's research efforts are based on both spin devices, as well as new transistor technologies.  Work on the latter is being conducted under the umbrella of the new DARPA/SRC STARnet center LEAST.  He is the recipient of an IBM Faculty Award and the best paper award at the IEEE Symposium on Nanoscale Architectures (2009).  Niemier has served on numerous technical program committees for design related conferences (including DAC, DATE, etc.), and was/is most recently the chair for the emerging technologies track at DATE and DAC.