Embedded System Design and Post-silicon Processor Validation/Debug

Preeti Ranjan Panda,   Department of Computer Science and Engineering, Indian Institute of Technology, Delhi, India

Abstract: During post-silicon processor validation, the state of the processor needs to be dumped out to a logic analyser so as to enable debug. Since the state is large (mostly L2 cache) and a lot of time is spent in the process of dumping. In this talk, I will explain a new compression mechanism that compresses debug data on its way out of the processor. In this work, the knowledge of the cache architecture is used to achieve high compression ratios, resulting in saving of logic analyser memory and dump time. Also, I will present how this proposed scheme can be used to significantly improve the reliability levels in the design of embedded processors.

About the speaker: Preeti Ranjan Panda received his B. Tech. degree in Computer Science and Engineering from the Indian Institute of Technology Madras, in 1990, and his M. S. and Ph.D. degrees in Information and Computer Science from the University of California at Irvine in 1995 and 1997 respectively. He is currently an Associate Professor in the Department of Computer Science and Engineering at the Indian Institute of Technology Delhi. He has previously worked at Texas Instruments, Bangalore (1990-1993) and the Advanced Technology Group at Synopsys Inc., Mountain View (1998-2002), and has been a visiting scholar at Stanford University (1999-2000).

His research interests are: Embedded Systems Design, CAD/VLSI, Post-silicon Debug/Validation, System Specification and Synthesis, Memory Architectures and Optimisations, Hardware/Software Codesign, and Low Power Design. He is the author of the book Memory issues in Embedded Systems-on-chip: Optimizations and Exploration, Kluwer Academic Publishers, 1999. He received an Honourable Mention Award at the International Conference on VLSI Design, Bangalore, 1992. He is a recipient of an IBM Faculty Award (2007) and a Department of Science and Technology Young Scientist Award (2003).

He has served on the program committees and chaired sessions at several conferences in the areas of CAD/VLSI and Embedded Systems: ICCAD, DATE, ASPDAC, CODES/ISSS, LCTES, VLSI-SoC, RTAS, VLSI Design, EUC, SBCCI, and VDAT. He is a member of the editorial board of ACM Transactions on Design Automation of Electronic Systems, International Journal of Parallel Programming (Springer) and VSI Vision.