A 5Ghz+ 128-Bit Binary Floating-Point Adder for the POWER6 Processor

Xiao Yan Yu, University of California, Davis, CA - USA

Abstract: A fast 128-bit end-around carry adder is designed and fabricated as part of the POWER6 floating-point unit in a 65nm SOI process technology. Efficient use of static circuits and careful balance of the look-ahead tree enable our floatingpoint design to operate beyond 5GHz with 1.1V supply.

 

About the speaker: Xiao Yan Yu is a member of ACSEL lab directed by Prof. Vojin G. Oklobdzija and as well as a staff arithmetic circuit designer at IBM Poughkeepsie site working on the core design of IBM's next-generation servers. Ms. Yu has received B.S.C.E. and M.S.E.E. degrees from University of California - Davis in 2001 and 2003 respectively and she's currently pursuing her Ph.D. at University of California - Davis.


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