Demystifying Ultra‐Low Power VLSI Design: from Basic Misconceptions to New Directions

Massimo Alioto, Associate Professor, Department of Information Engineering, University of Siena, Italy

Abstract: In the last few years, subthreshold VLSI circuits have become very popular in ultra‐low power applications such as distributed sensing, wearable computing, biomedical devices, green electronics. These applications typically constrain the power budget to a few μWs or less and the supply voltage to a few hundreds of mV. Operation at such low power/voltage poses very interesting challenges and offers new opportunities to develop emerging applications, as well as to stimulate and enable new technologies and markets.

In this seminar, basic concepts and advanced techniques for ultra‐low power (ULP) VLSI digital circuits and systems are presented, with emphasis on the related opportunities and challenges. For the first time, a unitary framework is presented to manage the energy‐performance‐ robustness tradeoff. Common misconceptions and incorrect beliefs are thoroughly discussed based on a coherent and fresh perspective on ULP VLSI circuits.

The seminar is organized as follows. Design constraints in ULP systems are preliminarily defined to understand the context, and the usually misunderstood role of energy and power in ULP applications is clarified. New design‐oriented circuit models are introduced to develop an intuitive sense of the robustness issues arising in Ultra‐Low Voltage (ULV) CMOS standard cells, and energy/voltage boundaries of CMOS VLSI circuits are explored. Variation‐aware design strategies to reduce the minimum operating voltage and enable robust ULV operation are then discussed. The dependence the minimum energy point on design knobs is discussed at various levels of abstraction, from physical to the micro‐architecture level. The effectiveness of various techniques to manage the related tradeoffs at those levels is discussed in a comprehensive manner, and general design guidelines are derived. In particular, the importance of pursuing performance even when targeting minimum energy is discussed in depth, and it is shown that ULP design and high performance design are actually two sides of the same coin. For the first time, robustness and yield are considered as further dimensions in the design space. The important (and often overlooked) role played by the minimum operating voltage is clarified, along with its relation with the optimal voltage minimizing energy, which is currently the subject of a controversial debate within the scientific community.

Finally, new directions and on‐going work to tackle the above challenges in extreme ULP systems will be presented. In particular, innovative smart on‐chip DC‐DC converters with high efficiency over a wide range of conditions will be presented, and the concept of “energy echoing” in extreme ULP applications will be introduced. Alternative logic styles will also be introduced to demonstrate reliable pW/gate operation, which enables perpetual circuit operation with mm‐ sized energy scavengers. An example of a fully functional wireless ULP platform in 65 nm will also be presented.


About the speaker: Massimo Alioto (M’01–SM’07) was born in Brescia, Italy, in 1972. He received the laurea degree in Electronics Engineering and the Ph.D. degree in Electrical Engineering from the University of Catania (Italy) in 1997 and 2001, respectively. In 2002, he joined the Information Engineering Department (Dipartimento di Ingegneria dell’Informazione - DII) of University of Siena. He was appointed Associate Professor of Electronics in 2005. He is the director of the Electronics Lab at University of Siena (site of Arezzo).  He is currently a visiting professor at the EECS Department of University of Michigan, Ann Arbor, working on ultra‐energy efficient resilient computing.

Prof. Alioto has been teaching undergraduate and graduate courses on advanced VLSI digital design, microelectronics and basic electronics. He is an IEEE Senior Member and a member of the HiPEAC Network of Excellence. He has authored or co‐authored more than 160 publications in journals (60, mostly IEEE Transactions) and conference proceedings. He is the co‐author of the book “Model and Design of Bipolar and MOS Current‐Mode Logic: CML, ECL and SCL Digital Circuits” (Springer, 2005). His primary research interests include ultra low‐power circuits for ubiquitous computing and self‐powered sensor nodes, active techniques for resilient energy‐ efficient computing and timing speculation, leakage‐ and variability‐aware design methodologies, circuit techniques in emerging technologies (FinFET, Tunnel FET, Ge and Si‐Ge MOS), Current‐ Mode Logic circuits, cryptographic circuits resistant to side‐channel attacks and ultra‐low power/area/design cost schemes for information security, low‐standby current caches.