Process aspect of increasing system level performance by 3D Integration

Deniz Sabuncuoglu Tezcan, IMEC (Interuniversity MicroElectronics Center), Leuven, Belgium

Abstract: Over the past 30 years and through scaling, the semiconductor industry has been able to continuously reduce the cost per function while simultaneously increasing the function density. However, technology roadblocks and the increased cost of ownership of scaled technology threaten to break this historic trend. Stacking of ICs and interconnecting them in the 3rd dimension, is an attractive alternative to 2D scaling that permits to continue system size reduction and to increase circuit performance while further reducing system cost. On the other hand, IC technology is specializing in different fields: microprocessors, memory, sensors, RF circuits and integration of these different technologies to make application specific systems becomes a challenge and 3D integration offers a solution. Many 3D integration schemes have been proposed in literature; and they can generally be classified according to the level at which the 3D interconnect breaks into the classical system interconnect hierarchy. Different technology platforms enable different 3D interconnect densities as well as a different electrical performance. Eventually, the different classes of 3D technologies will continue to co-exist since system requirements will dictate which technology options are viable for each specific application. Most of these 3D stacking "flavors" build on a combination of process technologies like wafer thinning, through wafer vias, dielectric isolation, conductive filling, bumping and flip-chip. The sequence and choice of the process technologies depend on the system level choices.

About the speaker: Deniz Sabuncuoglu Tezcan was born in Ankara, Turkey, in 1973. She received her B.S., M.S., and Ph.D. degrees in electrical engineering from Middle East Technical University (METU), Ankara, Turkey in 1995, 1997, and 2002, respectively. Her doctoral studies focused on uncooled infrared detectors implemented in CMOS technology. From 1995 to 2003, she was employed as a teaching/research assistant and later as an instructor in the Electrical and Electronics Engineering Department of METU. During her Ph.D., she was awarded with the Integrated Ph.D. Scholarship from the Scientific and Technical Research Council of Turkey (TUBITAK) to continue her studies partially at IMEC, Belgium and the Ph.D. Student Support Scholarship from ASELSAN Inc., Ankara, Turkey. In September 2003, she received the Post Doctoral Research Grant from Katholieke Universiteit Leuven, Belgium and continued her studies at IMEC. Since September 2005, she is employed by IMEC as Research Engineer specializing in process development and integration of various projects including 3D stacking of wafers/dies, through-wafer-vias for wafer level packaging, high performance active pixel CMOS imagers, Si:As blocked impurity band infrared detectors, wafer level liquid chromatographs and shock sensors. She is the author/co-author of more than 30 technical publications and has won the best paper award for "Development of Vertical and Tapered via Etch for 3D Through Wafer Interconnect Technology," at IEEE EPTC 2006.

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