Boolean Logic Representation for Emerging Devices

Tuesday, 13 May 2014 at 17:00 in INF 328

Anupam Chattopadhyay, RWTH Aachen, Germany

 

Abstract:

Representation of combinational Boolean logic has strong influence on a diverse range of problems such as, logic synthesis, circuit complexity analysis, logic verification and Boolean satisfiability checks. In this seminar, we will review two recently proposed logic representations namely, Bi-conditional Binary Decision Diagram (BBDD) and Majority Inverter Graph (MIG). Several theoretical results regarding these two structures will be discussed, e.g., complexity bounds, canonicity and identities for native transformations. In the second part of the seminar, mapping of these logic representations on emerging logic devices such as reversible logic and memristor will be discussed.

 

About the speaker:

Anupam Chattopadhyay received his B.E. degree from Jadavpur University, India in 2000. He received his MSc. from ALaRI, Switzerland and PhD from RWTH Aachen in 2002 and 2008 respectively. During his PhD, he worked on automatic RTL generation from the architecture description language LISA, which was commercialized later by CoWare (now part of Synopsys). In his doctoral thesis, he proposed a language-based modeling, exploration and implementation framework for partially re-configurable processors. From 2008 to 2010 he spent in CoWare R&D, as a member of consulting staff. He has published more than 40 technical papers, authored one book and several book-chapters in the above research areas. Since 2010, Prof. Dr.-Ing. Chattopadhyay is heading the research group of MPSoC Architectures in RWTH Aachen, Germany.