Process variations aware design

Wednesday, 22 February 2012 at 16h00, INF 328

Marc Pons, Integrated and Wireless Systems Group, CSEM, Neuchâtel

Abstract: In this seminar I will explain the work I have done during my PhD studies.

I have focused on the systematic process variations problem. First, I will briefly explain their sources and then what I have proposed to mitigate them, that is to maximize layout regularity.

My PhD contributions can be grouped in three major works:

• The proposal of a new regular layout fabric called VCTA (I will explain how VCTA layouts are constructed)
• The automation of the VCTA fabric (I will explain the automation flow proposed and the algorithms to minimize the final area of the VCTA layout)
• The layout regularity metric called FOCSI, and how it can be linked to variability (I will explain the benefits of layout regularity regarding systematic process variations)

About the speaker: Marc Pons received his M.Sc. in Telecommunications in 2005, from the Universitat Politecnica de Catalunya (Barcelona, Spain). Since 2006 he is a Ph.D. Student at the Electronic Engineering Department of the Universitat Politècnica de Catalunya. He is member of the HiPICs and ARCO research groups from the Electronic Engineering and Computer Architecture Departments of the Universitat Politècnica de Catalunya that collaborate with the Intel Barcelona Research Center (Barcelona, Spain). Since March 2011, he is finishing the Ph.D. at CSEM S.A, Division M, Integrated and Wireless Systems (Neuchâtel, Suisse). His research is focused on regular layouts to reduce the impact of process variations on integrated circuits for deep sub-micron CMOS technologies.