Thermal-Aware Synthesis

R. Iris Bahar, Division of Engineering, Brown University, Providence, RI - USA
Enrico Macii, Computer Engineering Department, Politecnico di Torino, Torino, Italy

Abstract: Increase in chip power density results in on-chip temperature increase, and thermal gradients (spatial and temporal) arise due to areas of the chip with different power dissipation (e.g., consequence of dynamic power management). High operating temperatures and non-negligible temperature variations (both in space and time) negatively affect normal operation of nanoscale circuits in various dimensions, including reliability (in the form of signal integrity problems and timing violations), leakage power, and delay (which are both dependent on temperature). For CMOS devices below 45nm these negative effects will likely be even more pronounced.

Mitigating the impact of temperature on modern integrated circuits is a complex and challenging task, since thermal effects can cause various components (e.g., logic gates, memory macros, wires, buses) to deviate from their nominal behavior. In addition, such deviations are "dynamic" by nature. That is, the amount of variation with respect to nominal behavior is not fixed, but instead depends on the temperature distribution across the die at any point in time.

Modeling thermal effects in silicon devices has been the subject of intensive research for a long time; however, this area of research is far from mature because we are actually aiming at a "moving target". Phenomena that seem to be well understood for a given process node become less predictable for technologies scaled to smaller dimensions; effects that are negligible for a given technology generation may have a dramatic impact on performance, power, reliability and manufacturability for subsequent generations.

In this talk, we present two examples of "thermal-aware" design. In particular, we first discuss a new methodology for thermal-aware clock tree synthesis based on the adoption of variable-delay buffers. Next, we describe a temperature-aware dual-Vt synthesis technique that reduces leakage power and guarantees timing correctness at the boundary temperatures provided by the technology library.

About the speakers: Iris Bahar received the B.S. and M.S. degrees in computer engineering from the University of Illinois, Urbana-Champaign, and the Ph.D. degree in electrical and computer engineering from the University of Colorado, Boulder. From 1987 to 1992, Prof. Bahar was with Digital Equipment Corporation, working on hardware processor implementation. Since 1996, she has been with the Division of Engineering, Brown University, in Providence, RI, where she is currently an Associate Professor. Her research interests include computer architecture; computer-aided design for synthesis, verification, and low-power applications; and design, test, and reliability issues for nanoscale systems. Prof. Bahar has been a member of the program committees of several international conferences, including International Conference on Computer-Aided Design (ICCAD), Design, Automation, and Test in Europe (DATE), and International Symposium on Low-Power Electronics Design (ISLPED). She is currently an Associate Editor of the IEEE Transactions on CAD and the ACM Journal of Emerging Technologies in Computing. This academic year she is spending a sabbatical at the Politecnico di Torino, working with Profs. Enrico Macii and Massimo Poncino on research problems related to power and thermal aware circuit design.

Enrico Macii is a Full Professor of Computer Engineering at Politecnico di Torino, Torino, Italy. His research interests are in the design automation of digital circuits and systems, with particular emphasis on low-power design aspects. In the fields above, he has authored over 300 scientific publications. He is the Editor-in-Chief of the IEEE Transactions on CAD/ICAS for the term 2006-2009. Prior to that, he was an Associate Editor for the same journal (1997-2005) and an Associate Editor for the ACM Transactions on Design Automation of Electronic Systems (2000-2005). He was the Technical Program Co-Chair (in 1999) of the IEEE Alessandro Volta Memorial Workshop on Low Power Design, the Technical Program Co-Chair (in 2000) and the General Chair (in 2001) of the ACM/IEEE International Symposium on Low Power Electronics and Design, the General Chair (in 2003) and the Technical Program Chair (in 2004) of the IEEE PATMOS Workshop, the General Co-Chair (in 2007) and the Technical Program Co-Chair (in 2008) of the ACM/IEEE Great Lakes Symposium on VLSI (GLS-VLSI). Enrico Macii is a Fellow of the IEEE, co-founder and member of the Board of Governors of the IEEE Council on Electronic Design Automation (CEDA).

 

Presentation slides with audio