Towards Variation Resilient Architectures

Pol Marchal, IMEC (Interuniversity MicroElectronics Center), Leuven, Belgium

Abstract: As electronics is becoming more mature, the technology development gets increasingly more complex and expensive. Whereas up to 2000 "scaling as usual" delivered extra performance, power and cost savings, it is unlikely that performance gains and power savings can be achieved in the future technology generations. Probably the greatest challenge caused by the nano-level scaling is the increase in the intra-die variability of the threshold voltage, drive and leakage current as they become dependent on the statistical distribution of parameters such as physical gate length and dopant concentration. The variability significantly impacts the circuit operation: the overdrive (V_dd-V_t) becomes very unpredictable even for neighboring identically sized transistors. As a result, the gate delay becomes a stochastic variable. This jeopardizes timing closure techniques. In SRAMs, device mismatch prevents V_dd scaling below 0.8V during read/write operation for yield and noise margin reasons, especially for bulk CMOS. These process variations increase relatively with scaling in the nanometric regime, with a rapid degradation of circuit-limited yield as a corollary. Platform architects will have to come up with new methods to design reliable electronic systems with uncertain components, and worst-case design must be avoided. One way to do this is by providing feedback controllers that minimize the impact of variability of the individual system components. In this presentation, we present IMEC's efforts in realizing such an architecture resilient against process variations.

About the speaker: Pol Marchal received the engineering degree and Ph.D. in electrical engineering from the Katholieke Universiteit Leuven, Belgium in 1999 and 2005 respectively. He currently holds a position as senior researcher at IMEC, Leuven.

Dr. Marchal's research interests are in all aspects of design of digital systems, with special emphasis on technology-aware design techniques for low-power systems.

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