Development of Novel Logic Design Techniques and Tools Based on Ambipolar Double Gate FET

29 May 2012 at 15h00 in INF 328

Kotb Jabeur, PhD Student, Lyon Institute of Nanotechnology, University of Lyon, France

 

Abstract:
The continuous growth of global demand with respect to semiconductor products (security, healthcare, entertainment, connectivity, energy, etc.) spanned a larger field where the impact of Moore’s law could be observed. That’s why, when CMOS technology scaling began to reach its theoretical limits, the ITRS has entered a new era known as “Beyond CMOS” concept to maintain the historical growth, doubled circuit density and increased performance. Novel materials and devices have been explored showing an ability to complement or even replace the CMOS transistor or its channel in systems on chip with silicon-based technology. The intensive research in new devices and materials has lead the way to the recognition of some original phenomena, such as the ambipolar conduction in quasi one- and zero-dimensional structures; for example in carbon nanotubes, graphene and silicon nanowires. Ambipolarity, in a dual-gate context (DG-FETs), means that n- and p-type behavior can be observed in the same device depending on the back gate voltage polarity. In addition to their attractive performances and the low power consumption, ambipolar double gate devices open the way to novel circuits and design paradigms. Conventional logic synthesis techniques cannot represent the capability of DG-FETs to operate as either n-type or p-type switches and new techniques must be found to build optimal logic.

The work in this thesis paves the path for designers using such devices by defining generic approaches and design techniques based on ambipolar DG-FET. Two different contexts are tackled; the first deals with the use of ambipolar DG-FET to improve standard cells logic design with more compact structures and better performance as well as describing low-power design techniques exploiting the fourth terminal of the device. The second context deals with reconfigurability purposes by adapting conventional logic synthesis and verification techniques such as Binary Decision Diagrams or Functions Classes to ambipolar devices in order to build reconfigurable logic cells. Methods and techniques described along this dissertation, are validated and evaluated in a case study focused on DG-CNTFET through accurate simulations using the most mature and recent DG-CNTFET model available in literature.
 

About the Speaker:

Kotb Jabeur was born in Teboulba, Tunisia in 1984. He received the Engineer degree in Electrical Engineering from ENIM-Monastir, Tunisia, in 2008, and the M.S. degree from INSA Lyon, France, in 2009. He joined the Lyon Institute of Nanotechnology, University of Lyon (INL-ECL) in October 2009 as a Ph.D. student working under the supervision of Prof. Ian O'Connor. He will defend his thesis in September 2012.

He is currently involved in the Nanograin project. His research activities and interests are focused on the development of novel logic design techniques and tools based on Ambipolar Double Gate FETs.