Nanowires from 1D to 3D devices and memories

Thomas Ernst, CEA-LETI, Grenoble, France

3D CMOS nanowire matrices and 2D thin film technologies recently developed, enable not only sub-22nm CMOS device scaling, but also ultimate co-integration of novel functionalities [1-3]. For CMOS scaling, Silicon-On-Insulator (SOI) or innovative Silicon-On-Nothing (SON) based 3D nanowires are proposed with common or independent gates. Ultra-low static consumption, as well as high driving current were achieved thanks to 3D stacked Gate-All-Around (GAA) nanowire channels. The top-down nanowire techniques also open up new opportunities for hybridizing CMOS with novel functionalities such as 3D memories, nano-oscillators and bio nano-sensors.

[1] T. Ernst et al. IEDM 2006, 2008
[2] A. Hubert et al, IEDM 2009
[3] K. Tachi et al, IEDM 2009

About the speaker:  Thomas Ernst received his Ph.D. degrees from the National Polytechnics Institute of Grenoble, France, in 2000. From 1997 to 2000, he developed advanced SOI CMOS electrical characterization, simulation and modeling methods at STMicroelectronics and IMEP laboratory. He then joined CEA-LETI to develop novel strained-channel CMOS architectures for 32 nm technology. In particular, he was leading strained SOI, strained Germanium, and SiGeOI CMOS integration at LETI. Since 2005, he is leading the 3D multi-channels and nanowire CMOS devices developments. His expertise is in the area of novel CMOS device fabrication technology and MOSFETs analytical modeling for electrical characterization. Dr. Ernst is author or co-author of over 130 technical journal papers and communications at international conferences on CMOS device integration, modeling and characterization. He is author or co-author of more than 16 patents. He is a member of ESSDERC and ULIS conferences technical committees since 2005 and member of IEDM TPC for 2 years. He is a recipient of research grant from the European Research Council to develop multi-physics integrated systems.