Early Chip Planning for Thermal and Power-Supply Issues

*** SEMINAR HAS BEEN CANCELLED ***

Early-stage chip design is generally performed by a few experts with years of experience and the help of spreadsheets. However, modern designs are running into problems and constraints on multiple fronts, driving the complexity that must be considered at an early design stage beyond what can be handled using simple tools. This talk will cover our current work on the Early Chip Planner, a tool that we have developed to enable early-stage designers to compare design options using multiple complex physical-design-oriented metrics, such as thermal and power-supply performance, as well as traditional metrics like area and timing.

About the speakers:
Jeonghee Shin is a Research Staff Member at IBM T. J. Watson Research Center. She is currently working on early processor design automation and 3D chip planning. Her research interests are in the area of design automation, productivity, and computer architecture. Jeonghee received her PhD degree in Computer Engineering at the University of Southern California in 2008, focusing on lifetime reliability-aware design and modeling, and interconnection networks.

Michael B. Healy received his Ph.D. in Computer Engineering from the Georgia Institute of Technology in December, 2010. His dissertation research focused on physical design techniques and methods to increase or examine thermal and power-supply reliability in microarchitectural designs, with a focus on 3D integration. In October, 2010, he entered IBM as a post-doctoral researcher. His research interests focus on 3D technology and all of the potential benefits and problems that it poses for the semiconductor community.