Energy Recovery VLSI

Marios Papaefthymiou, Electrical Engineering and Computer Science Department, University of Michigan, Ann Arbor

Abstract: Three decades ago theoretical physicists suggested that the controlled recovery of charge could yield electronic circuitry that dissipates significantly less power than conventional CMOS. Early work in this field, which became generally known as adiabatic computing, focused on the asymptotic energetics of computation, yielding reversible designs that approach thermodynamic limits of energy efficiency when operating at arbitrarily slow speeds. In this talk, I will first give a brief overview of energy recovery design. I will then move on to describe several energy recovery chips that have been designed in my research group at Michigan. Giving up on reversibility, these chips operate fast while enabling the recovery of a substantial fraction of their power. Designed in a 0.13um bulk silicon process with on-chip inductors, the fastest of these chips achieve clock rates in excess of 1GHz and energy recovery rates in the 60% to 80% range.

About the speaker: Marios Papaefthymiou is Professor of EECS and Director of the Advanced Computer Architecture Laboratory at the Univesity of Michigan. He received his PhD from Massachusetts Institute of Technology in 1993 and joined Michigan in 1996, after a 3-year term as Assistant Professor at Yale University. His research interests are currently focused on ultra-low power computer design.

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