Self-Calibrating Networks-on-Chip

Frédéric Worm, PhD Student at EPFL-IC-LAP

 

Abstract: Networks-on-chip provide an elegant framework to efficiently reuse pre-designed cores. However, reuse of cores is jeopardized by new deep sub-micron noise effects that challenge reliability of CMOS technology. Moreover, noise margins are further reduced as supply voltage scale down. We advocate that self-calibrating techniques will be needed to maintain acceptable design trade-off between energy, performance, and reliability. As a result, self-calibrating techniques have to be integrated within networks-on-chip. This paper presents a self-calibrating link and discusses qualitatively the problem of controlling adaptively its voltage and frequency.


Download visuals (pdf 96 KB)