Embedded Computing Challenges:

Architecture and Design

Giuseppe Desoli, Advanced Systems Technology Group, STMicroelectronics, Milan, Italy

Abstract: Modern systems on a chip are reaching prohibitively large design and verification costs; this in turn, associated with higher mask costs, imposes larger volumes requirements than in the past, which conflicts even more with tight time to market and rapid obsolescence of products caused by the quick market shifts from one standard to the other de facto or otherwise; the promise of the advent of megagate SoC designs is then hindered by such complexity and to start reaping the benefits associated with it, more regularity must go into the system designs associated to more programmability and reconfigurability.
More programmability could address the cost of late discovery of critical bugs, adapt to changing standards, improve, given the suitable simulation technology is used, the overlap for software and firmware development with the SoC design itself, it even has a future potential for improving yield by way of redundancy of computing elements if excess capacity can be afforded, and much more.

New computing engines and platforms for next generation of computing systems in advanced nanometer technologies are being proposed; although such discussion is at an early stage and far from being complete, some basic fundamental concepts on Communication centric computing architectures and Design for Manufacturing (DFM), regularity, distributed processing, and software interaction are presented. This talk tries to address some of these innovative topics, in order to elaborate and define new research directions for a novel architecture-to-silicon platform for advanced computing systems, where the driving concept of manufacturing based on regularity is analyzed at different level of abstractions, from software and architecture, till fabrication.

About the speaker: Giuseppe Desoli graduated in Electronics Engineering from the University of Genoa, Italy in 1991 (summa cum laude) where he also received a PhD in Telecommunications in 1995, working in the field of parallel architectures and algorithms for signal and image processing, he joined as a computer scientist HP Labs at the Cambridge Lab in Massachusetts, USA from 1995 to 2002, doing research in VLIW architectures with a special focus on embedded custom defined microprocessors, tools and binary translation technologies, working together with some of the most influential pioneers of the field. He later came to STMicroelectronics, attracted by practical application of VLIW processors platforms to embedded devices and SoCs, and he currently leads a microprocessors research group within the advanced system technology R&D group of STM. He's co-authored more than 50 scientific publications on both computer science and signal processing and he holds a number of patents with both the European and US patent offices.
 

Software Mapping

Marco Cornero, Director of Compilers, Operating Systems and Applications, STMicroelectronics, Milan, Italy

Abstract: Although regularity helps in the design and programming at subsystem level, the overall embedded SoC's will remain highly heterogeneous, in order to accommodate the stringent cost requirements. In fact, in the future we will move from the current heterogeneous multi-processor systems, to heterogeneous multi-multi-processors, making the software mapping problem even more difficult than before. Solving such a problem in a single step is way too ambitious. What is needed is rather a kind of system-level assembly model to start handling the complexity in a coherent manner, to then gradually evolve towards a more abstract model with associated tools. In our talk we will focus on software components as a first step towards better software abstractions and tools for heterogeneous SoC's.
Another serious concern, affecting current and future embedded systems, is the considerable limitations in productivity of embedded software development derived from the high fragmentation of embedded processors and associated tools. Instruction-set virtualization techniques have been investigated for a long time to address this issue, with mixed results, especially for what concerns performance overhead. In our presentation we will present our virtualization approach which is specifically focused on high performance for our advanced embedded processors.

About the speaker: Marco Cornero, Ph.D., Director of Compilers, Operating Systems and Applications. Ten years of industrial experience in tools for advanced microprocessors and embedded systems. Ph.D. at the University of Genova, Italy, on CAD technologies for high-level synthesis, in cooperation with IMEC - Belgium. At STMicroelectronics since 1995, working on compilers for several ST architectures, including the ST200 VLIW family, in cooperation with HP Labs Cambridge. Currently manager of three main activities, namely compiler development for advanced architectures, operating systems and applications for embedded parallel processors.