Tuesday, 16 December 2014 at 11:00 in INF 328

Beyond-Memory Applications for Memristive Nano-Crossbar Arrays

Eike Linn, Institute of Materials in Electrical Engineering and Information Technology II, RWTH Aachen University, Aachen, Germany
Vikas Rana, Forschungszentrum, Juelich, Germany

 

Abstract:

Resistive switching devices, also called memristive devices, are considered one of the most promising candidates for future non-volatile memories. They offer an ultimate scaling potential down to 5 nm, are suitable for passive crossbar arrays of minimum area (4 F²), and are highly compatible with common CMOS technology for realizing hybrid circuits. By applying an appropriate select device at each cross-point junction, either a rectifying element or a complementary resistive switch (CRS), large-scale arrays are feasible.

Complementary Resistive Switches inherently comprise a matched selector and memory device, thus offer a highly promising approach to realize memory and logic functionality in a single device. For vertically stacked TaO_x-based CRS devices excellent scalability, high endurance and low current operation could be shown recently.

Besides the potential as memory, memristive crossbar arrays offer implementation of memory-intensive computing paradigms. First, CRS arrays enable implementation of multi-parallel search algorithms for pattern recognition tasks. Second, the non-volatility of the devices enables ‘stateful’ logic-in-memory operations. These logic operations are directly processed in the memory and arithmetic tasks, e.g. additions, are carried out within the array. Thus, by blurring the boundaries between memory and arithmetic logic units the von-Neumann-bottleneck can be eased. CRS logic operations were experimentally verified using quasi-static sweeps and pulses. Moreover, the results were confirmed by simulations using a dynamical memristive switching device models.

The availability of accurate memristive circuit models is a crucial factor for further development of computing concepts for memristive arrays, thus, the detailed knowledge of the dynamic behavior of the actual resistive switch is essential. For Ag or Cu-based electrochemical metallization (ECM) a one-state-variable ECM model is used, whereas for valence change mechanism (VCM) cells (typical materials: TiO_x, TaO_x or HfO_x) a more complex approach is required. A three-part check for model consistency reveals the limitations of over-simplistic memristor models: This simple check comprises the pulse height dependency of the SET voltage, the impact of series resistors on the low resistive state, and the qualitative I-V behavior in complementary cell configuration.
 

About the speakers:

Eike Linn works for RWTH Aachen University, Aachen, Germany as research associate at Institute of Materials in Electrical Engineering and Information Technology II (IWE II). He works within the framework of the Jülich Aachen Research Alliance for Future Information Technology (JARA-FIT). He received the Diploma degree in electrical engineering from RWTH Aachen University, Aachen, Germany, in 2006. In 2012 he received the Ph.D. degree in electrical engineering from RWTH Aachen University, Aachen, Germany (summa cum laude). Since 2013 his work is sponsored by the German Research Foundation (DFG) under grant LI 2416/1-1: Novel Computer-Architectural Concepts Arising from Complementary Resistive Switch Enhanced Passive Crossbar Arrays. He is reviewer for several journals (IEEE EDL, IEEE TED, IEEE TCAS, IEEE Nano, IEEE TIE, Microelectron. Eng., Microelectron. J., Semicond. Sci. Technol., Sci. Rep., PSS, PNAS, Plos one, RSC Nanoscale). In 2010 he introduced the concept of complementary resistive switches (CRS) to overcome the sneak path obstacle in passive crossbar arrays. His publications have been cited > 400 times according to ISI web of science. His research interests include development of new logic-in-memory and neuromorphic concepts for ReRAM-based crossbar array memories.
 

Vikas Rana works at Forschungszentrum, Juelich, Germany, as a senior scientist. He is responsible for the technological developments for ReRAM device and integration. His current research activities are focused on transition metal-oxides based nanoscale ReRAM devices and integration with the advanced CMOS technology (1T-1R). He holds Master of Technology degree in Solid State Physics from Indian Institute of Technology, Delhi and a Ph.D. in Electrical Engineering from Delft University of Technology, Netherlands.