Logic Synthesis for Majority based In-Memory Computing

Wednesday, 14 September 2016 at 16:15 in room INF 328

Saeideh Shirinzadeh, PhD student, Computer Architecture Group (AGRA), University of Bremen, Germany

 

Abstract:

The resistive switching property exhibited by many emerging memory technologies enables the execution of logic operations within memory arrays. This opens up new horizons to a modern era of computer architectures beyond the traditional Von Neumann architectures which have separated memory and computing units. Resistive memories possess an intrinsic majority property which can be exploited efficiently for synthesis of logic-in-memory computing circuits and systems. In this talk, a customized in-memory computing synthesis approach as well as a Programmable Logic-in-Memory (PLiM) architecture, both based on the resistive majority property, will be introduced and their optimization will be discussed considering the latency and area issues.

About the speaker:

Saeideh Shirinzadeh is a PhD student at the group of Computer Architecture (AGRA) at University of Bremen since June 2014. She has done her B.Sc. and M.Sc. in electrical engineering at University of Guilan, Iran in 2010, and 2012, respectively. Her research interests include optimization of data structures, evolutionary computation, logic synthesis and in-memory computing.