3D monolithic integration

Perrine Batude, CEA-LETI, Grenoble, France

Abstract: 3D integration generates great interest to solve the fundamental limits of scaling e.g. increasing delay in interconnections, development costs and variability. 3D monolithic integration, by opposition to parallel (or back-end or TSV 3D integration) is the only technological option enabling to fully benefit from the third dimension potential at the transistor scale thanks to its high alignment precision (σMONO ~10nm compared to σTSV ~0.5µm ). The sequential processing of bottom and top FET is however challenging because of the potential detrimental impact on bottom FET of the top FET processing. During this presentation, an overview of  Leti’s results in that field will be given [1][2][3].

[1] P. Coudrain et al, IEDM 2008
[2] P.Batude et al, VLSI 2009
[3] P.Batude et al, IEDM 2009

About the speaker: Perrine Batude received her M.S degree in physics and engineering from ENSPG Institute (Institut National polytechnique de Grenoble), Grenoble, France. During her Ph.D. obtained in 2009, she worked on the development of 3D monolithic integration in CEA-Leti. She joined LETI in 2009 as a device engineer in the Electronics Nanodevices Laboratory. In the frame of these activities, she received the best student paper awards in INFOS 2007, Athens; in ICICDT 2008, Grenoble; and in IEDM 2009, Baltimore.