The Migration of Safety-Critical Real-Time Software to Multicore

Wednesday, 9 July 2014 at 14:15 in INF 328

Marco Caccamo, University of Illinois, Urbana-Champaign, IL, USA

 

Abstract:

Building safety-critical real-time systems out of inexpensive, non-realtime, COTS components is challenging. Although COTS components generally offer high performance, they can occasionally incur significant timing delays. To prevent this, we propose two approaches: 1) a new "clean slate" real-time, memory-centric scheduling theory; and 2) a framework of novel application-transparent, kernel-level techniques to perform fine-grained resource reservation of cache space and memory bandwidth in multi-core real-time systems.

We have successfully implemented and tested the proposed framework on a commodity ARM-based system and on a Freescale P4080 platform; it can also be applied to a variety of other platforms currently available on the market. Finally, experimental benchmark results show that employing the proposed techniques to eliminate (last level) cache and memory bandwidth interference can avoid more than 2X slowdown of measured worst-case execution time.

About the speaker:

Marco Caccamo received a Ph.D. in Computer Engineering from Scuola Superiore Sant'Anna, Italy in 2002. He is currently a Professor at the Department of Computer Science, University of Illinois at Urbana-Champaign. He has authored/coauthored more than 80 refereed publications in real-time and embedded networked computing systems. He is Guest Editor of the Journal of Real-Time Systems; he was Program Chair of RTAS, and later General Chair of RTAS and Cyber Physical Systems Week (CPSWeek) 2011. His research interests include real-time systems, cyber-physical systems, real-time scheduling and resource management, real-time networks, and quality of service control in next generation digital infrastructures. He is a senior member of IEEE.