October 3, 2016

Adaptive Voltage Scaling Techniques for Dynamic Variation Tolerance in Digital ICs

Monday, 3 October 2016 at 11:00 in room INF 328

Weiwei Shan, Associate Professor, School of Electronic Science & Engineering, Southeast University, Nanjing, China


Abstract:

Power consumption is now regarded as one of the top concerns in digital IC design. Low power techniques are very important in increasing battery life (especially for portable devices) and reliability. In-situ timing monitoring based adaptive voltage scaling (AVS) is an effective way to improve IC performance or reduce power. Timing error prediction such as canary flip-flop has advantages of small overhead due to no error recovery, which is especially useful for non-CPU or non-replayable ICs. Enabling the IC to operate over a wide voltage range helps to improve energy efficiency while satisfying varying performance demands. However, it brings new challenges due to severe and widely variable PVT variations in near-threshold voltage, causing the required detection window vary a lot across a wide voltage range, plus the critical paths to be monitored increases a lot too.

This talk will present some recent results of adaptive voltage scaling techniques based on in-situ timing error monitoring for digital SoCs, especially our design using adaptive detection window tuning and monitored paths optimization to solve the problems caused by variable PVT variations due to wide-operating-range.
 

About the speaker:

Weiwei Shan is an associate professor at the School of Electronic Science & Engineering, Southeast University, Nanjing, China. She received the Ph.D. degree in Microelectronics from Tsinghua University, China in January 2009. She visited University of Maryland, College Park, US during August 2007 - August 2008 and IMEC, Belgium during August-September 2016. She has published nearly 40 papers in journals and conferences and won a national scientific award. Her research interests mainly focus on low power techniques for digital IC and SCA-resistance techniques for crypto circuits.