A Unified HW/SW Interface Model to Remove Discontinuities Between HW and SW Design

Ahmed Jerraya, TIMA Laboratory, Grenoble, France

Abstract: Modern SoC (System on Chip) may include one or several CPU sub-systems to execute software and sophisticated interconnect in addition to specific hardware sub-systems. SoC are generally application specific and require efficient HW/SW interfaces design.

Abstract HW-SW Interfaces are extensively used to coordinate software and hardware communities for the design of classic computers. Abstract HW-SW Interfaces allow concurrent design of complex systems made of sophisticated software and hardware platforms. Examples include API at different abstraction levels, RTOS libraries, drivers, typically summarized as hardware dependent software. This abstraction smoothes the design flow and eases interaction between different teams belonging to different cultures, hardware, software and system architecture. In this classical scheme, HW/SW interfaces are modelled twice. HW designers use a HW/SW interface model to test their hardware design, and software designers use a HW/SW interface model to validate the functionality of their software. The use of two separate models induces a discontinuity between hardware and software. This generates cost and performances overheads that are not acceptable for SoC design. A single HW/SW interface needs to be shared between both hardware and software designers since the early stage of SoC design.
 

HW-SW interfaces abstraction levels

This presentation deals with a unified HW/SW model to describe different parts of HW/SW interface at different abstraction levels. The benefits of using the proposed model are two fold: first, it provides a single model to present system design from abstract specification to mixed HW/SW implementation and second, it enables full system simulation at different abstraction level during refinement flow.

About the speaker: Dr. Jerraya has the grade of Research Director within the CNRS and is currently managing the System-Level Synthesis group of TIMA Laboratory where he is working on application specific multiprocessor System on Chip.

Dr. Ahmed Amine Jerraya received the Engineer degree from the University of Tunis in 1980 and the D.E.A., "Docteur Ingénieur", and the "Docteur d'Etat" degrees from the University of Grenoble in 1981, 1983, and 1989 respectively, all in computer sciences. In 1986, he held a full research position with the CNRS (Centre National de la Recherche Scientifique). From April 1990 to March 1991, he was a Member of the Scientific Staff at Nortel in Canada, working on linking system design tools and hardware design environments.

He served as the General Chair of DATE 2001 and co-founded the International Seminar on Multi-Processor SoC held every year in July. He co-authored 6 books and more than 200 papers in International Conferences and Journals. He received the Best Paper Award at the 1994 ED&TC for his work on Hardware/Software Co-simulation.
 

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