Communications-Inspired Design of Nanometer SoCs

Naresh Shanbhag, Department of Electrical and Computer Engineering, University of Illinois, Urbana-Champaign, IL - USA

Abstract: Scaling of feature sizes into the nanometer regime has lead to the emergence of the power-reliability wall, which threatens the continuation of Moore's Law. Energy-efficiency and reliability though intimately intertwined have historically been addressed by disparate communities; I will describe a communications-inspired design paradigm for nanometer ICs in general, and communication ICs in particular, that has the potential to breach the power-reliability wall. This paradigm is based on the view that nanometer SOCs are miniature communication networks; a view first proposed in our 1997 publication and later endorsed by the 1999 and subsequent International Technology Roadmap Semiconductors. Key elements of this paradigm are the use information-theory to determine bounds on energy-efficiency of nanometer circuits in the presence of noise and other non-idealities, and the use of communication-theoretic techniques such as equalization and error-control for on-chip computation, communication, storage as well as for mixed-signal analog front-end design in order to approach these bounds. The talk will demonstrate communications-inspired designs of on-chip computation and communication sub-systems.

About the speaker: Naresh R. Shanbhag received his Ph.D. degree from the University of Minnesota in 1993 in Electrical Engineering. From 1993 to 1995, he worked at AT&T Bell Laboratories at Murray Hill where he was the lead chip architect for AT&T's 51.84 Mb/s transceiver chips over twisted-pair wiring for Asynchronous Transfer Mode (ATM)-LAN and very high-speed digital subscriber line (VDSL) chip-sets. Since August 1995, he is with the Department of Electrical and Computer Engineering, and the Coordinated Science Laboratory at the University of Illinois where he is presently a Professor. His research interests are in the design of integrated circuits and systems for broadband communications including low-power/high-performance VLSI architectures for error-control coding, equalization, as well as digital integrated circuit design. He has numerous publications in this area and holds three US patents. He is also a co-author of the research monograph Pipelined Adaptive Digital Filters published by Kluwer Academic Publishers in 1994.

Dr. Shanbhag became an IEEE Fellow in 2006, received the 2001 IEEE Transactions on VLSI Best Paper Award, the 1999 IEEE Leon K. Kirchmayer Best Paper Award, the 1999 Xerox Faculty Award, the Distinguished Lecturership from the IEEE Circuits and Systems Society in 1997, the National Science Foundation CAREER Award in 1996, and the 1994 Darlington Best Paper Award from the IEEE Circuits and Systems Society. From 1997-99 and from 1999-2002, he served as an Associate Editor for the IEEE Transaction on Circuits and Systems: Part II and the IEEE Transactions on VLSI, respectively. He is currently serving on the technical program committees of major international conferences such as the International Solid-State Circuits Conference (ISSCC), the International Conference on Computer-Aided Design (ICCAD), the International Symposium on Low-Power Design (ISLPED), the International Conference on Acoustics, Speech and Signal Processing (ICASSP), the IEEE Signal Processing Systems Workshop (SiPS), and the International Symposium on Circuits and Systems (ISCAS).

Dr. Shanbhag is a co-founder (along with Dr. Singer) and Chief Technology Officer of Intersymbol Communications, Inc., a venture-funded fables semiconductor start-up that provides mixed-signal ICs for electronic dispersion compensation for optical links. Intersymbol Communications, Inc., was acquired by Kodeos Communications, Inc., in 2006 and is presently a wholly-owned subsidiary of the latter.