Design and Implementation of Body Area Wireless Sensor Networks

David Atienza, Embedded Systems Laboratory (ESL), Swiss Federal Institute of Technology, Lausanne

Abstract: In this presentation the design and implementation of wireless body area sensor networks for biomedical monitoring will be covered. In particular, the presentation focuses on the details of the operating system based design and embedded systems tools for the exploration and customization of the wireless communication protocols. This design enables to achieve very low power features of the nodes and guarantees message priorities between the different nodes communicating in the network. Furthermore, the limitations of the existing operating systems and implementation details will be outlined. The features and necessary optimizations of the signal processing applications to be ported and executed in the microcontrollers used in wireless body area sensor networks will also be covered in this seminar.

About the speaker: David Atienza is Professor and Director of the Embedded Systems Laboratory (ESL) at the Institute of Electrical Engineering within the School of Engineering (STI) of EPFL, Switzerland. He also holds the position of Adjunct Professor at the Computer Architecture and Automation Department of Complutense University of Madrid (UCM), Spain. Additionally, he is currently Scientific Counselor of long-time research of Inter-University Micro-Electronics Center Nederland (IMEC-NL), Holst Centre, Eindhoven, The Netherlands. He received his M.Sc. and Ph.D. degrees in Computer Science from Complutense University, Madrid, Spain, and Inter-University Micro-Electronics Center (IMEC), Leuven, Belgium, in 2001 and 2005, respectively.

His research interests focus on design methodologies for integrated systems and high-performance embedded systems, including new modelling frameworks to explore thermal management techniques for Multi-Processor System-on-Chip, novel architectures for logic and memories in forthcoming nano-scale electronics, dynamic memory management and memory hierarchy optimizations for embedded systems, Networks-on-Chip interconnection design, and low-power design of embedded systems.