- H. Riener, R. Ehlers, B. Schmitt and G. De Micheli, "Exact Synthesis of ESOP Forms", in R. Dreschler and M. Soeken Editors,
*Advanced Boolean Techniques*, Springer 2019. - I. Tzouvadaki, G. De Micheli and S. Carrara, "Memristive Biosensors for Ultrasensitive Diagnostics and Therapeutics", in M. Suri, Editor,
*Applications of Emerging Memory Technology*, Springer 2019.

- P.-E. Gaillardon, J. Zhang, L. Amarù and G. De Micheli.
*Multiple-Independent-Gate Nanowire Transistors: From Technology to Advanced SoC Design*, in Nano-CMOS and Post-CMOS Electronics: Devices and Modeling, num. Volume 1, 2015. - A. Cavallini, C. Boero, G. De Micheli and S. Carrara.
*CNT and proteins for bioelectronics in personalized medicine*, in Hand Book of Bioelectronics: Directly Interfacing Electronics and Biological Systems, Part II, Chapter 9, p. 109-121, 2015. - G. De Micheli.
*Electronic systems for health management*, in Handbook of Bioelectronics: Directly Interfacing Electronics and Biological Systems, Part VIII, Chapter 42, p. 543-549, 2015. - X. Tang, S. Rahimian Omam, P. Meinerzhagen, P.-E. Gaillardon and G. De Micheli.
*Low Power FPGAs based on Resistive Memories*, in Reconfigurable Logic: Architecture, Tools and Applications, pp. 399-432, CRC Press, 2015. - I. Taurino, A. Sanginario, G. De Micheli, D. Demarchi and S. Carrara.
*Carbon Nanomaterials for Electrochemical and Electrochemiluminescent Medical Sensors*, in Carbon for Sensing Devices, Chapter 6, Springer 2015.

- D. Sacchetto, P.-E. Gaillardon, Y. Leblebici and G. De Micheli.
*Memory Effects in Multi-Terminal Solid State Devices and their Applications*, in Memristor Networks, p. 429-472, 2014.

- C. Seiculescu, S. Murali, L. Benini and G. De Micheli.
*3D Network on Chip Topology Synthesis: Designing Custom Topologies for Chip Stacks*, in A. Sheibanyrad, F. Pétrot, A. Jantsch, Editors, 3D Integration for NoC-based SoC Architectures, num. 3, p. 193-223, Springer 2011. - C. Seiculescu, S. Murali, L. Benini and G. De Micheli.
*Design and Analysis of NoCs for Low-Power 2D and 3D SoCs*, in C. Silvano, M. Lajolo, G. Palermo, Editors, Low Power Networks-on-Chip, num. 3, p. 199-222, Springer 2011. - H. Ben Jamaa and G. De Micheli.
*Reliable Circuit Design with Nanowire Arrays*, in C. Jha, D. Chen, Editors, Nanoelectronic Circuit Design, p. 153-188, Springer 2011. - C. Baj-Rossi, G. De Micheli, and S. Carrara,
*P450-Based Nano-Bio-Sensors for Personalized Medicine*, in P. A. Serra, Editor, Biosensors for Health, Environment and Biosecurity / Book 1, Intech, 2011.

- V. Rana, D. Atienza Alonso, M. D. Santambrogio, D. Sciuto, and G. De Micheli,
*A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication,*in C. Piguet, R. Reis, and D. Soudris, Editors,VLSI-SoC: Design Methodologies for SoC and SiP, IFIP Advances in Information and Communication Technology, pp. 232-250, Germany: Springer, 2010.

- H. Ben Jamaa, B. K. Boroujeni, G. De Micheli, Y. Leblebici, C. Piguet, A. Schmid, and M. Stanisavljevic.
*Design Technologies for Nanoelectronic Systems Beyond Ultimately Scaled CMOS*, in G. De Micheli, Y. Leblebici, M. Gijs, J. Vörös, Editors, Nanosystems Design and Technology, volume Chapter 3, pages 45-84. Springer, 2009.

- S. Murali, P. Meloni, F. Angiolini, D. Atienza, S. Carta, L. Benini, G. De Micheli, and L. Raffo,
*Designing Routing and Message-Dependent Deadlock Free Networks on Chips*, in G. De Micheli, S. Mir, R. Reis, Editors, VLSI-SoC: Research Trends in VLSI and Systems on Chip, vol. 1, pp. 337-356, London: Springer, 2008.

- L.Benini and G.De Micheli,
*Networks on Chip: A new Paradigm for component-based MPSoC Design,*in A. Jerraja and W.Wolf Editors, "Multiprocessor Systems on Chips", Morgan Kaufmannn, 2004, pp. 49-80. - L.Benini, D. Bertozzi and G.De Micheli,
*Energy-Efficient Network on Chip Design,*in E. Macii Editor, Ultra Low Power Electronics and Design, Kluwer, 2004, pp.214-232. - D. Bertozzi, L. Benini and G.De Micheli,
*Network on Chip Design for Gigascale Systems on Chips*, in R. Zurawski, Editor, Industrial Technology Handbook, CRC Press, 2004, pp. 95.1-95.18 on Chips, Morgan Kaufmannn, 2004, pp. 49-80. - T. Ye, L. Benini and G.De Micheli,
*Networks on Chip Design of SoC Interconnection*, in C. Piguet, Editor, Low Power Electronics Design, CRC Press, 2004, pp.30.1-30.16 - G.De Micheli,
*Networking Chip Subsystems,*in Yearbook 2004, McGraw-Hill, pp.224-226.

- D. Bertozzi, L. Benini and G. De Micheli,
*Error Control Schemes for On-chip Interconnection Networks: Reliability versus Energy Efficiency,*in A. Jantsch and H. Tenhunen, Editors, "Networks on Chip", Kluwer

- L. Benini and G. De Micheli,
*Energy-efficient System-level Design,*in J. Rabaey and M. Pedram, Editors, "Power-Aware Design Methodologies", Kluwer, pp. 473-516 - L. Benini and G. De Micheli,
*Logic Synthesis for Low Power,*in S. Hassoun and T. Sasao, Editors, "Logic Syntesis and Verification", Kluwer, pp. 197-223

- G. De Micheli,
*Cell-based Logic Optimization,*

- G. De Micheli, L. Benini and A. Bogliolo,
*Dynamic Power Management of Electronic Systems,*in A. Jerraya and J. Mermet, Editors, "System-level Synthesis", Kluwer, pp. 263-292

- C. Coelho and G. De Micheli,
*Modeling and Synthesis of Synchronous System-Level Specifications,*in J. Berge, O. Levia and J. Rouillard, Editors, "Models in System Design", Vol. 9, Kluwer Academic Publishers, pp. 1-47

- G. De Micheli,
*Hardware/Software Co-design: Application Domains and Design Technologies,*in G. De Micheli and M. Sami, Editors, "Hardware/Software Co-design", Kluwer Academic Publishers, pp. 1-28

- G. De Micheli,
*High-Level Synthesis of Digital Circuits**,*in M. Yovits, Editor, "Advances in Computers", Vol. 37, pp. 208-285, Academic Press, and Stanford University Report, CSL-TR-92-551, November 1992.

- D. Ku and G. De Micheli,
*Synthesis of ASICs with Hercules and Hebe**,*in R. Camposano and W. Wolf, Editors, "Trends in High-Level Synthesis, Kluwer, pp. 177-203, and Stanford University Report, CSL-TR-91-461, February, 1991. - D. Ku and G. De Micheli,
*High-Level Synthesis and Optimization Stategies in Hercules and Hebe**,*in P. Michel and G. Saucier, Editors, "Logic and Architecture Synthesis", North Holland, pp. 111-120 - M Damiani and G. De Micheli,
*Efficient Computation of the Exact and Approximate Observability Don't Care Sets in Multiple-Level Logic Synthesis,*in P. Michel and G. Saucier, Editors, "Logic and Architecture Synthesis", North Holland, pp.209-218, and Stanford University Report, CSL-TR-90-424

- R. Brayton, R. Camposano, G. De Micheli, R. Otten and J. Van Eijndhoven,
*The Yorktown Silicon Compiler System,*in D. Gajski, Editor, "Silicon Compilation", pp. 204-310, Addison Wesley and IBM Report, No. RC 12500

- G. De Micheli, H.Y. Hsieh and I. Hajj,
*Decomposition Techniques for Large Scale Circuits,*in A. Ruehli, Editor, "VLSI Circuit Analysis, Simulation and Design", North Holland, Vol. 2, pp. 1-39 and IBM Research Report, No. RC 11712 - G. De Micheli,
*Design of Control Systems,*in G. De Micheli, A. Sangiovanni-Vincentelli and P. Antognetti, Editors, "Design Systems for VLSI Circuits: Logic Synthesis and Silicon Compilation", Martinus Nijhoff, pp. 327-364 and IBM Research Report, No. RC 12062

- G. De Micheli, M. Hoffman, A.R. Newton and A. Sangiovanni-Vincentelli,
*A Design System for PLA-based Digital Circuits,*in A. Sangiovanni-Vincentelli, Editor, "Advances in Computer Engineering Design", Jai press, pp. 285-364