Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits

Speaker: Dr. Vasilis F. Pavlidis, Integrated Systems Laboratory (LSI), Swiss Federal Institute of Technology, Lausanne

Abstract
Three-dimensional (3-D) or vertical integration is a promising design paradigm to overcome the existing interconnect bottleneck in integrated systems. The opportunities and the manufacturing and design challenges related to this novel technology are briefly reviewed. Specific interconnect and physical design methodologies for vertically integrated systems are discussed. An efficient and accurate technique for placing the vertical interconnects thereby improving the circuit speed is presented. Global interconnect architectures for 3-D circuits, such as 3-D networks-on-chip are proposed and evaluated. Other global issues, such as synchronization and power distribution, are also discussed. A 3-D prototype circuit investigating several clock distribution network topologies is presented. Finally, the opportunities offered by TSVs to improve power integrity in 3-D circuits are discussed.

Short Biography
Vasilis F. Pavlidis is currently a post-doc at LSI-EPFL, Switzerland. He received the Ph.D. degree from the Electrical and Computer Engineering Department at the University of Rochester, New York, USA in 2008 under the supervision of Prof. Eby Friedman. He received the B.S. and M.Eng. in electrical and computer engineering from the Democritus University of Thrace, Xanthi, Greece, in 2000 and 2002, respectively. From 2000 to 2002, he was with INTRACOM S.A., Athens, Greece. During summer 2007, he interned at Synopsys Inc, Mountain View, USA. His current research interests are in the area of interconnect modeling, 3-D integration, networks-on-chip, and related design issues in VLSI. He is the co-author of the book on Three-Dimensional Integrated Circuit Design.