Post-doctoral Researcher
Integrated Systems Laboratory
Swiss Federal Institute of Technology, Lausanne, Switzerland
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Process Variation Effects in 3-D Clock Distribution Networks

This talk emphasizes the effect of manufacturing variations on the design of 3-D integrated systems. Including both the within-die and die-to-die process variations, a statistical model that describes the variability of skew within 3-D clock distribution networks is proposed. Both the systematic and random components of process variations are considered in this model. Several 3-D clock distribution topologies are analyzed using this model. The susceptibility of these topologies to process variations is shown to change considerably. Design guidelines are offered and new 3-D clock distribution networks that result in lower process-induced skew variation are proposed.

About the speaker:
Dr. Vasilis Pavlidis was born in 1976 in Kavala, a picturesque city northeast of Greece. He grew up in Athens where he spent most of his teen years. He received the Bachelor’s and Master’s degrees from the Electrical and Computer Engineering department of the Democritus University of Thrace, Xanthi, Greece. In September of 2002, he joined the ECE department of the University of Rochester, Rochester, NY, USA. Under the supervision of Professor Eby G. Friedman, he received his Master's degree in 2003 and PhD degree in 2008 from the University of Rochester. He joined the Integrated Systems Laboratory at EPFL as a post-doctoral researcher in September 2008.

His broader research interests are in the area of interconnect design and analysis, IC design, and related design methodologies:
• 3-D integrated circuit design
• Interconnect modeling, analysis, and design
• Process variations effects on integrated circuit design
• Mixed-signal circuit design