Workshop Schedule

Click here to download workshop schedule.

Monday, 16 January 2012
8:30 - 10:00	CAD Challenges in a Mobility Driven Era Noel Menezes Intel Corporation, Hillsboro, Oregon, USA
10:00 - 10:30	Coffee & Discussion
10:30 - 12:00	Device and Circuit Considerations for sub-22nm Technologies Kaushik Roy Purdue University, West Lafayette, Indiana, USA
12:00 - 12:30	Discussion
12:30 - 14:00	Lunch
14:00 - 15:30	ASIP: The (too) long way from academia to product Heinrich Meyr RWTH Aachen University of Technology, Germany
15:30 - 16:30	Coffee & Discussion
Tuesday, 17 January 2012
8:30 - 10:00	Capturing, Modelling and Leveraging Process Variability in IC Design Costas Spanos University of California at Berkeley, California, USA
10:00 - 10:30	Coffee & Discussion
10:30 - 12:00	Design technologies for next-generation heterogenous many-core platforms Luca Benini STMicroelectronics/University of Bologna, Italy
12:00 - 12:30	Discussion
12:30 - 14:00	Lunch
14:00 - 15:30	Static timing for the other 99% Larry Jones Synopsys Inc., Mountain View, California, USA
15:30 - 16:30	Coffee & Discussion
Wednesday, 18 January 2012
9:30 - 10:00	The Swiss Nano-Tera Program Martin Rajman Nano-Tera Executive Director
10:00 - 10:30	Coffee
10:30 - 12:00	The Early Days of CMOS VLSI Design and CAD; Back to the Future Steve Kang University of California, Santa Cruz, California, USA
12:00 - 12:30	Discussion
12:30 - 14:00	Lunch
14:00 - 15:30	Can Higher-Level Abstraction Help in Crossing the Brick Wall of Complexity? Rob Roy Atrenta Inc, San Jose, California, USA
15:30 - 16:30	Coffee & Discussion
Thursday, 19 January 2012
10:00 - 10:30	Coffee
10:30 - 12:00	Energy Efficient Designs with Wide Dynamic Range Vivek De Intel Corporation, Hillsboro, Oregon, USA
12:00 - 12:30	Discussion
12:30 - 14:00	Lunch
14:00 - 15:30	Protocol Verification in SOC Designs - An Industrial Experience John Moondanos University of Thessaly, Volos, Greece
15:30 - 16:30	Coffee & Discussion
Friday, 20 January 2012
8:30 - 10:00	Scaling Trends of Energy Efficient, Low Voltage Operations David Blaauw University of Michigan, Ann Arbor, Michigan, USA
10:00 - 10:30	Coffee & Discussion
10:30 - 12:00	Measuring and enhancing the reliability of CMOS circuits Sachin Sapatnekar University of Minnesota, Minneapolis, Minnesota, USA
12:00 - 12:30	Discussion
12:30 - 14:00	Lunch
14:00 - 15:30	Are guardbanding and overdesign viable under 20nm? The case of voltage integrity George Stamoulis University of Thessaly, Volos, Greece
15:30 - 16:30	Coffee & Discussion

 

Please see links given above for talk abstracts.

General Outline and Goals

Breakthroughs in integrated circuit processing technology have enabled the uninterrupted shrinking of silicon devices beyond 20nm. However, this came at the price of new design hurdles that need to be overtaken in the form of new design constraints that current design methodologies and CAD tools are ill-equipped to handle efficiently. Most importantly, CAD tools and methodologies, instead of being used to further enhance the performance gains and power savings inherent in every new process node, are hampering the exploitation of the process’ potential, leading to ever decreasing performance and power gains. The overdesign and guardbanding required by current design methodologies and imposed in part because of the disconnect between CAD tools and current design issues, and in part because of the increased anxiety and cost of a failed tapeout. This is leading into a dead-end situation in which methodology and tool imposed constraints on a design would swamp out the gains of moving into a new process. We need to “reinvent” the design process based on new CAD tools that meet the needs of today’s design teams.

It is widely accepted that there exists a stagnation in the electronic design automation (EDA) industry, which has hurt both the ability of extracting the maximum performance and power out of new process technologies, especially in the sub-45nm region, as well as the bottom line of EDA companies, which have seen their share of the total design budget shrink over the past five years. This is due to the fact that most design tools have had their basic functionalities crystallized in the 1980’s, with few breakthroughs making it to the mainstream since. However, the problems designers face have changed significantly since then. New design hurdles have arisen, with what were considered second order effects at the inception of current EDA tools becoming the major problems to be addressed. What were considered “reliability” issues have come to the forefront: voltage drop on the power supply network, thermal gradients and hot spots, transistor aging, inductive effects, electromigration, and signal integrity issues take up a major part of the design effort, significantly influencing the major design parameters of delay and power. The standard treatment of such issues through guardbanding and overdesign has run its course, and new solutions are required as designs drift ever further from the optimal with every process generation. Further complicating the aforementioned design issues are a) process variation, which is significantly larger in sub-45nm technologies and b) lithography effects that make circuit characterization significantly more complex as the minimum feature length becomes comparable to the light source wavelength. On the other hand, processing power and memory capacity are enabling solutions that were not possible even five years ago in simulation, modeling, and optimization technologies, which in tandem with new theoretical and algorithmic breakthroughs will enable at least 2X improvement in circuit performance, power, and reliability over those delivered by the current state-of-the-art methodologies and CAD tools.