Assistant Professor
Department of Electrical Engineering and Computer Science
Stanford University, Stanford, CA - USA
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Lecture 1: Thursday, 17 July 2008 (14h00-15h00) CO3

Carbon Nanotube Transistor Circuits: Opportunities, Challenges, and Experimental Demonstration
One-dimensional nanodevices such as Carbon Nanotube Field-Effect Transistors (CNFETs) are promising candidates as extensions to Si CMOS due to excellent device performance. A major gap exists between such single-device-level results and techniques required to harness the science into practical design technologies competitive with silicon-CMOS. An "ideal" CNFET technology can enable digital designs with 13X Energy-Delay-Product (EDP) advantage compared to 32nm Si-CMOS with same lithographic ground rules. However, fundamental challenges prevent us from creating efficient CNFET-based robust computing fabrics with anywhere close to above benefits. This talk will discuss major opportunities and challenges with CNFETs, and describe an interdisciplinary approach to overcome the challenges by combining imperfection-immune design techniques with CNFET modeling and processing. We will also present experimental demonstration of essential components and their integration for large-scale CNFET technology.


Lecture 2: Wednesday, 16 July 2008 (15h15-16h15) CO3

Imperfection-Immune Carbon Nanotube VLSI Logic Circuits

Carbon Nanotube Field-Effect Transistors (CNFETs) are promising candidates as extensions to silicon-CMOS for two major reasons:
1. CNFETs can provide significant energy and performance benefits over traditional CMOS, and 2. CNFET processing is compatible with existing CMOS processing flows.
Two fundamental barriers that prevent us from creating digital designs at VLSI scale using CNFETs are: 1. Misaligned and mis-positioned Carbon Nanotubes (CNTs), and 2. Metallic CNTs.
Misaligned and mis-positioned CNTs can result in incorrect logic implementations. Metallic CNTs create resistive source-drain shorts in CNFETs, causing excessive leakage, severely degraded noise margins, and delay variations. In this paper, we introduce an imperfection-immune design paradigm to overcome these barriers. We present a design technique, together with experimental demonstration, for creating CNFET logic circuits that are guaranteed to implement correct functions even in the presence of a large number of misaligned and mis-positioned CNTs. We also describe techniques for co-optimizing CNT processing and circuit design in order to derive practical design guidelines for metallic-CNT-tolerant digital circuits. These techniques are very inexpensive compared to traditional defect- and fault-tolerance techniques, do not impose major changes in VLSI design flows, and are compatible with VLSI processing because they do not require special customization on a chip-by-chip basis.


About the speaker:
Subhasish Mitra is an Assistant Professor in the Departments of Electrical Engineering and Computer Science of Stanford University. He leads the Stanford Robust Systems Group with research focus on robust system design in scaled CMOS and emerging nanotechnologies. Prior to joining Stanford, he was a Principal Engineer at Intel Corporation.

Prof. Mitra invented design and test techniques that have seen wide spread proliferation in the chip design industry. His X-Compact technique for test compression is used by more than 50+ Intel products and is supported by major CAD tools. His major awards include the NSF CAREER Award, Terman Fellowship, IEEE CAS Donald O. Pederson Award (IEEE Trans. CAD Best Paper Award), ACM