Other Publications (with limited distribution)

2003

  1. W. Qadeer, T. Simunic, J. Ankorn, V. Krishnan and G. De Micheli, Heterogeneous Wirel;ess network Management PACS - WOrkshop on Power-Aware Computer Systems, San Diego, December 2003.

2002

  1. E.Y. Chung, L. Benini, G. De Micheli,G. Luculli and M. Carilli, Value-sensitive Automatic Code Specialization for Energy Reduction, ST Journal of System Research, Vol. 3, No. 1, pp. 29-48

2000

  1. E. Y. Chung, L. Benini and G. De Micheli, , Energy Efficient Source Code Transformations based on Value Profiling, Proceedings of the International Workshop on Compilers and Operating Systems for Low Power, Philadelphia, October 2000
  2. L. Semeria, K. Sato, and G. De Micheli, Memory Representation and Hardware Synthesis of C Code with Pointers and Complex Data Structures, SASIMI '00, Proceedings of the Synthesis and Simulation Meeting and International Exchange, Kyoto, Japan, pp. 43-48

1999

  1. L. Benini, A. Bogliolo and G. De Micheli, System-level Dynamic Power Management, Proceedings Volta Memorial Conference, Como, pp. 23-31
  2. M. Barocci, L. Benini, A. Bogliolo, B. Ricco and G. De Micheli, Look-up Table Power Macro-models for Behavioral Library Components, Proceedings Volta Memorial Conference, Como, pp.173-181

1998

  1. L. Semeria and G. De Micheli, Encoding of Pointers for Hardware Synthesis, Proceedings of the Logic and Architecture Workshop, Grenoble

1997

  1. L. Benini, G. De Micheli, E. Macii, M. Poncino and R. Scarsi, Integrating Logic-level Power Management Techniques, SASIMI '97, Proceedings of the Synthesis and Simulation Meeting and International Exchange, Osaka, Japan, pp. 59-65
  2. L. Benini and G. De Micheli, Dynamic Power Management of Electronic Circuits and Systems, SASIMI '97, Proceedings of the Synthesis and Simulation Meeting and International Exchange, Osaka, Japan, pp. 3-10
  3. A. Bogliolo, L. Benini, G. De Micheli and B. Ricco, Stima di potenza nella progettazione di circuiti integrati a basso consumo, AEI Annual Meeting, pp. 137-142, Baveno (in Italian)
  4. L. Benini, G. De Micheli, E. Macii and M. Poncino, Telescopic Units: a New Paradigm for Performance Optimization of VLSI Design, International Logic Synthesis Workshop, Tahoe City, CA
  5. V. Bertacco, S. Minato, P. Verplaetse, L. Benini and G. De Micheli, Decision Diagrams and Pass-Transistor Logic Synthesis, International Logic Synthesis Workshop, Tahoe City, CA
  6. L. Benini, G. De Micheli, E. Macii, M. Poncino, S. Quer, D. Sciuto, C. Silvano, On-Going Research on Address Bus Encoding for Low Power: A Status Report, International Logic Synthesis Workshop, Tahoe City, CA

1996

  1. A. Bogliolo, L. Benini, D. Guan, D. Ku and G. De Micheli, Open Distributed EDA Environments on the Web, SASIMI '96, Proceedings of the Synthesis and Simulation Meeting and International Exchange, Fukuoka, Japan, pp. 47-56

1995

  1. L. Benini and G. De Micheli, A Survey of Boolean Matching Techniques for Library Binding, Proceedings of the Logic and Architecture Workshop, Grenoble
  2. L. Benini, M. Favalli and G. D Micheli, Generalized Matching: a New Approach to Concurrent Logic Optimization and Library Binding, International Logic Synthesis Workshop
  3. L. Benini and G. De Micheli, Optimal Synthesis of Gated-Clocks for Low-Power Finite-State Machines, International Logic Synthesis Workshop

1993

  1. C. Coelho, D. Ku and G. De Micheli, An Algebra for Modeling Concurrent Digital Systems, TAU, ACM International Workshop on Timing Issues, Malente, Germany, September 1993
  2. J. Fron, J. Yang, M. Damiani and G. De Micheli, A Synthesis Framework Based on Trace and Automata Theory, International Workshop on Logic Synthesis, 5c-1, 5c-15, May 1993

1992

  1. D. Ku, D. Filo, C. Coelho and G. De Micheli, Interface Optimization for Concurrent Systems Under Timing Constraints using Interface Matching, International High-Level Synthesis Workshop, Dana Point, California, November 1992, pp. 202-213
  2. R. Gupta, C. Coelho and G. De Micheli, Program Implementation Schemes for Hardware-Software Systems, ACM Workshop on Hardware-Software Co-design, October, 1992
  3. G. De Micheli, Synthesis of High-Performance Digital Circuits: Logic Transformations for Cycle-Time Reduction of Synchronous Circuits, SASIMI '92, Proceedings of the Synthesis and Simulation Meeting and International Exchange, Kobe, Japan, April 1992, pp. 133-142
  4. A. Bedarida, S. Ercolani and G. De Micheli, A New Technology mapping Algorithm for the Design and Evaluation of Field-Programmable Gate Arrays, ACM International Workshop on Field-Programmable Gate Arrays, February 1992, pp. 103-108

1991

  1. M. Damiani and G. De Micheli, Derivation of Don't Care Conditions by Perturbation Analysis of Combinational Multiple-Level Logic Circuits, International Logic Synthesis Workshop, Raleigh, May 1991, pp. 1-12
  2. D. Filo, D. Ku and G. De Micheli, Optimizing Control by Delayed Execution of Operations, International High-Level Synthesis Workshop, Buelerhoehe, Germany, March 1991, pp. 118-125

1990

  1. M. Damiani and G. De Micheli, The Role of Don't Care Conditions in Synchronous Circuit Optimization, SASIMI '90, Proceedings of the Synthesis and Simulation Meeting and International Exchange, Kyoto, Japan, pp. 55-62

1989

  1. G. De Micheli, Synchronous Logic Synthesis, International Workshop on Logic Synthesis, Research Triangle Park, May
  2. G. De Micheli and A. Ruehli, Switching-time of MOS Transistors in Presence of Inductive Effects, IBM Technical Disclosure Bulletin, Vol. 31, No. 8, January 1989, pp. 447-448

1987

  1. R. Brayton and G. De Micheli, A Method for Minimizing Critical Timing of a Digital System, IBM Technical Disclosure Bulletin, Vol. 30, No. 2, July 1987, pp.586-589