Other Publications (with limited distribution)

Giovanni De Micheli

2023

  1. S.-Y. Lee, H. Riener and G. De Micheli, Customizable On-the-fly Design Space Exploration for Logic Optimization of Emerging Technologies, International Logic Synthesis Workshop (IWLS), Lausanne 2023
  2. A. Costamagna, A.Mishchenko and G. De Micheli, The Combinational-Complexity Game For Symmetric Functions, International Logic Synthesis Workshop (IWLS), Lausanne 2023
  3. A. Tempia Calvino and G. De Micheli, Technology Mapping Using Multi-output Library Cells, International Logic Synthesis Workshop (IWLS), Lausanne 2023
  4. D. Marakkalage, M. Walter, S.-Y. Lee, R. Wille and G. De Micheli, Technology Mapping for Beyond-CMOS Circuitry with Unconventional Cost Functions, International Logic Synthesis Workshop (IWLS), Lausanne 2023
  5. A.Mishchenko, R. Brayton, A.Tempia-Calvino, and G. De Micheli, Boolean Decomposition Revisited, International Logic Synthesis Workshop (IWLS), Lausanne 2023

2022

  1. S.Y.Lee, H. Riener and G. De Micheli, External dont cares in logic synthesis, International workshop on Boolean Problems, Bremen, 2022
  2. D. Marakkalage and G. De Micheli Fanout-Bounded Logic Synthesis for Emerging Technologies - A Top- Down Approach, International Workshop on Logic Synthesis (IWLS) 2022.
  3. A.Tempia Calvino and G. De Micheli, Depth-optimal Buffer and Splitter Insertion and Optimization in AQFP Circuits, International Workshop on Logic Synthesis (IWLS) 2022.
  4. S.-Y. Lee, H. Riener and G.De Micheli An Automated Testing and Debugging Toolkit for Gate-Level Logic Synthesis Applications, International Workshop on Logic Synthesis (IWLS) 2022.
  5. H. Wang, S.-Y. Lee and G. De Micheli A Cost-generic Resubstitution Algorithm with Customizable Cost Functions, International Workshop on Logic Synthesis (IWLS) 2022

2021

  1. H. Riener, S.-Y. Lee, A. Mishchenko and G.De Micheli Boolean Rewriting Strikes Back: Reconvergence- Driven Windowing and Resynthesis, International Workshop on Logic Synthesis (IWLS) 2021
  2. S.-Y. Lee, H. Riener, and G.De Micheli Irredundant Buffer and Splitter Insertion and Scheduling- Based Optimization for AQFP, International Workshop on Logic Synthesis (IWLS) 2021 and ArXiv http://arxiv.org/abs/2109.00291
  3. D. Marakkalage, H.Riener and G.i De Micheli Optimizing Adiabatic Quantum-Flux-Parametron (AQFP) Circuits using Exact Methods, International Workshop on Logic Synthesis (IWLS) 2021
  4. A. Tempia Calvino, H. Riener, S.Rai and G. De Micheli From Logic to Gates: A Versatile Mapping Approach to Restructure Logic, International Workshop on Logic Synthesis (IWLS) 2021

2020

  1. S.-Y. Lee, H. Riener, A. Mishchenko, R. Brayton, G. De Micheli, Simulation-Guided Boolean Resubstitution, IWLS 2020, San Francisco, USA, July 2020.
  2. S. Rai, H. Riener, G. De Micheli, A. Kumar, XMG-based Logic Synthesis for Emerging Reconfigurable Nanotechnologies, IWLS 2020, San Francisco, USA, July 2020.
  3. D. S. Marakkalage, E. Testa, H. Riener, A. Mishchenko, M. Soeken, G. De Micheli, Three-Input Gates for Logic Synthesis, IWLS 2020, San Francisco, USA, July 2020.

2019

  1. H. Riener, E. Testa, W. Haaswijk, A. Mishchenko, L. Amaru, G. De Micheli, and M. Soeken, Logic Optimization of Majority-Inverter Graphs, Workshop MBMV, Kaiserslautern, Germany, April 8-9, 2019.
  2. E.Testa, W. Haaswijk, M. Soeken, G. De Micheli: The Complexity of Self-Dual Monotone 7-Input Functions, 28th International Workshop on Logic & Synthesis (IWLS), Lausanne, Switzerland, June 21-23, 2019.
  3. F. Mozafari, M. Soeken, G. De Micheli, Automatic Preparation of Uniform Quantum States Utilizing Boolean Functions, 28th International Workshop on Logic & Synthesis (IWLS), Lausanne, Switzerland, June 21-23, 2019.

2014

  1. L. Amarù, A. Balatsoukas Stimming, P.-E. Gaillardon, A. Burg and G. De Micheli, Restructuring of Arithmetic Circuits with Biconditional Binary Decision Diagrams, University Booth at DATE 2014 (Design, Automation & Test in Europe), Dresden, Germany, 2014.
  2. L. Amarù, P.-E. Gaillardon and G. De Micheli, Majority Logic Representation and Satisfiability, 23rd International Workshop on Logic & Synthesis (IWLS), San Francisco, California, USA, 2014.

2003

  1. W. Qadeer, T. Simunic, J. Ankorn, V. Krishnan and G. De Micheli, Heterogeneous Wirel;ess network Management PACS - WOrkshop on Power-Aware Computer Systems, San Diego, December 2003.

2002

  1. E.Y. Chung, L. Benini, G. De Micheli,G. Luculli and M. Carilli, Value-sensitive Automatic Code Specialization for Energy Reduction, ST Journal of System Research, Vol. 3, No. 1, pp. 29-48

2000

  1. E. Y. Chung, L. Benini and G. De Micheli, , Energy Efficient Source Code Transformations based on Value Profiling, Proceedings of the International Workshop on Compilers and Operating Systems for Low Power, Philadelphia, October 2000
  2. L. Semeria, K. Sato, and G. De Micheli, Memory Representation and Hardware Synthesis of C Code with Pointers and Complex Data Structures, SASIMI '00, Proceedings of the Synthesis and Simulation Meeting and International Exchange, Kyoto, Japan, pp. 43-48

1999

  1. L. Benini, A. Bogliolo and G. De Micheli, System-level Dynamic Power Management, Proceedings Volta Memorial Conference, Como, pp. 23-31
  2. M. Barocci, L. Benini, A. Bogliolo, B. Ricco and G. De Micheli, Look-up Table Power Macro-models for Behavioral Library Components, Proceedings Volta Memorial Conference, Como, pp.173-181

1998

  1. L. Semeria and G. De Micheli, Encoding of Pointers for Hardware Synthesis, Proceedings of the Logic and Architecture Workshop, Grenoble

1997

  1. L. Benini, G. De Micheli, E. Macii, M. Poncino and R. Scarsi, Integrating Logic-level Power Management Techniques, SASIMI '97, Proceedings of the Synthesis and Simulation Meeting and International Exchange, Osaka, Japan, pp. 59-65
  2. L. Benini and G. De Micheli, Dynamic Power Management of Electronic Circuits and Systems, SASIMI '97, Proceedings of the Synthesis and Simulation Meeting and International Exchange, Osaka, Japan, pp. 3-10
  3. A. Bogliolo, L. Benini, G. De Micheli and B. Ricco, Stima di potenza nella progettazione di circuiti integrati a basso consumo, AEI Annual Meeting, pp. 137-142, Baveno (in Italian)
  4. L. Benini, G. De Micheli, E. Macii and M. Poncino, Telescopic Units: a New Paradigm for Performance Optimization of VLSI Design, International Logic Synthesis Workshop, Tahoe City, CA
  5. V. Bertacco, S. Minato, P. Verplaetse, L. Benini and G. De Micheli, Decision Diagrams and Pass-Transistor Logic Synthesis, International Logic Synthesis Workshop, Tahoe City, CA
  6. L. Benini, G. De Micheli, E. Macii, M. Poncino, S. Quer, D. Sciuto, C. Silvano, On-Going Research on Address Bus Encoding for Low Power: A Status Report, International Logic Synthesis Workshop, Tahoe City, CA

1996

  1. A. Bogliolo, L. Benini, D. Guan, D. Ku and G. De Micheli, Open Distributed EDA Environments on the Web, SASIMI '96, Proceedings of the Synthesis and Simulation Meeting and International Exchange, Fukuoka, Japan, pp. 47-56

1995

  1. L. Benini and G. De Micheli, A Survey of Boolean Matching Techniques for Library Binding, Proceedings of the Logic and Architecture Workshop, Grenoble
  2. L. Benini, M. Favalli and G. D Micheli, Generalized Matching: a New Approach to Concurrent Logic Optimization and Library Binding, International Logic Synthesis Workshop
  3. L. Benini and G. De Micheli, Optimal Synthesis of Gated-Clocks for Low-Power Finite-State Machines, International Logic Synthesis Workshop

1993

  1. C. Coelho, D. Ku and G. De Micheli, An Algebra for Modeling Concurrent Digital Systems, TAU, ACM International Workshop on Timing Issues, Malente, Germany, September 1993
  2. J. Fron, J. Yang, M. Damiani and G. De Micheli, A Synthesis Framework Based on Trace and Automata Theory, International Workshop on Logic Synthesis, 5c-1, 5c-15, May 1993

1992

  1. D. Ku, D. Filo, C. Coelho and G. De Micheli, Interface Optimization for Concurrent Systems Under Timing Constraints using Interface Matching, International High-Level Synthesis Workshop, Dana Point, California, November 1992, pp. 202-213
  2. R. Gupta, C. Coelho and G. De Micheli, Program Implementation Schemes for Hardware-Software Systems, ACM Workshop on Hardware-Software Co-design, October, 1992
  3. G. De Micheli, Synthesis of High-Performance Digital Circuits: Logic Transformations for Cycle-Time Reduction of Synchronous Circuits, SASIMI '92, Proceedings of the Synthesis and Simulation Meeting and International Exchange, Kobe, Japan, April 1992, pp. 133-142
  4. A. Bedarida, S. Ercolani and G. De Micheli, A New Technology mapping Algorithm for the Design and Evaluation of Field-Programmable Gate Arrays, ACM International Workshop on Field-Programmable Gate Arrays, February 1992, pp. 103-108

1991

  1. M. Damiani and G. De Micheli, Derivation of Don't Care Conditions by Perturbation Analysis of Combinational Multiple-Level Logic Circuits, International Logic Synthesis Workshop, Raleigh, May 1991, pp. 1-12
  2. D. Filo, D. Ku and G. De Micheli, Optimizing Control by Delayed Execution of Operations, International High-Level Synthesis Workshop, Buelerhoehe, Germany, March 1991, pp. 118-125

1990

  1. M. Damiani and G. De Micheli, The Role of Don't Care Conditions in Synchronous Circuit Optimization, SASIMI '90, Proceedings of the Synthesis and Simulation Meeting and International Exchange, Kyoto, Japan, pp. 55-62

1989

  1. G. De Micheli, Synchronous Logic Synthesis, International Workshop on Logic Synthesis, Research Triangle Park, May
  2. G. De Micheli and A. Ruehli, Switching-time of MOS Transistors in Presence of Inductive Effects, IBM Technical Disclosure Bulletin, Vol. 31, No. 8, January 1989, pp. 447-448

1987

  1. R. Brayton and G. De Micheli, A Method for Minimizing Critical Timing of a Digital System, IBM Technical Disclosure Bulletin, Vol. 30, No. 2, July 1987, pp.586-589