Design and Management of Vertically Stacked Memory for 3-D Multi-Processors

Thursday, 7 November 2013 at 14:00 in INF 328

Kyungsu Kang, Integrated Systems Laboratory, EPFL

 

Abstract:
3-D integrated circuits (3-D IC) with through-silicon-via (TSV) technology offers a promising solution to overcome the limitations of device scaling. The 3-D fabrication technology makes it possible to stack several homogeneous or heterogeneous memory dies onto a multi-core die in order to improve the power efficiency, resulting with shortened on-chip wires as well as reduced off-chip memory access times. However, many challenges still exist, such as larger TSV footprint, higher power density, etc.

This talk consists of three parts; 1) a circuit-switched mesh-of-tree interconnect will be introduced for extremely low-latency communication among processing cores and multiple memory banks stacked on the multi-core die. 2) A runtime power management scheme (e.g., voltage and frequency scaling, power gating, etc.) will be introduced for the management of operating temperature, focusing on the performance improvement of 3-D chip-multiprocessor. 3) Design and management of hybrid SRAM-MRAM cache using heterogeneous memory stacking will also be introduced briefly in the view of system-level design.

About the Speaker:
Kyungsu Kang received the unified degrees of MS and PhD from the Department of Electrical Engineering of KAIST, Korea in 2010. Since 2011 he has been working as a post-doctoral researcher at the Integrated Systems Laboratory (LSI) of EPFL with Prof. Giovanni De Micheli. Previously, he worked with Prof. Chong-Min Kyung as a post-doctoral researcher at KAIST. His research interests include system-level design methodologies for 3-D ICs, low-power design and thermal-aware design.