Assistant Professor
Robust Sytsems Group, Director
Departments of Electrical Engineering and Computer Science
Stanford University, Stanford, CA - USA
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Robust System Design

Today’s mainstream electronic systems typically assume that transistors and interconnects operate correctly over their useful lifetime. With enormous complexity and significantly increased vulnerability to failures compared to the past, future system designs cannot rely on such assumptions. At the same time, there is explosive growth in our dependency on such systems. For example, in 2009, a glitch in a single circuit board of the air-traffic control system resulted in hundreds of flights being canceled or delayed.

Robust system design is essential to ensure that future systems perform correctly despite rising complexity and increasing disturbances. For coming generations of silicon technologies, several causes of hardware failures, largely benign in the past, are becoming significant at the system-level.  Furthermore, emerging nanotechnologies such as carbon nanotubes are inherently highly subject to imperfections.

With extreme miniaturization of circuits, factors such as transient errors, device degradation, and variability induced by manufacturing and operating conditions are becoming important. While design margins are being squeezed to achieve high energy efficiency, expanded design margins are required to cope with variability and transistor aging. Even if error rates stay constant on a per-bit basis, total chip-level error rates grow with the scale of integration. Moreover, difficulties with traditional burn-in can leave early-life failures unscreened.

This talk will address the following major robust system design goals:
•    New approaches to thorough post-silicon validation that scale with tremendous growth in complexity
•    Cost-effective tolerance and prediction of failures in hardware during system operation
•    A practical way to overcome substantial inherent imperfections in emerging nanotechnologies.

Significant recent progress in robust system design impacts almost every aspect of future systems, from ultra-large-scale computing and storage systems, all the way to their nanoscale components.
 

About the speaker:
Prof. Subhasish Mitra directs the Robust Systems Group in the Department of Electrical Engineering and the Department of Computer Science of Stanford University. Before joining Stanford, he was a Principal Engineer at Intel Corporation.

Prof. Mitra’s research interests include robust system design, VLSI design, CAD, validation and test, and emerging nanotechnologies. His X-Compact technique for test compression has been used in more than 50 Intel products, and has influenced major CAD tools.  The IFRA technology for post-silicon validation, created jointly with his student, was characterized as “a breakthrough” in the Communications of the ACM. His work on the first demonstration of imperfection-immune carbon nanotube VLSI circuits, jointly with his students and collaborators, was selected by NSF as a Research Highlight to the US Congress, and was highlighted as “a significant breakthrough” by the Semiconductor Research Corporation and the MIT Technology Review.

Prof. Mitra’s major honors include the Presidential Early Career Award for Scientists and Engineers from the White House, the highest US honor for early-career outstanding scientists and engineers, ACM SIGDA Outstanding New Faculty Award, IEEE CAS/CEDA Pederson Award for the IEEE Transactions on CAD Best Paper, IEEE/ACM Design Automation Conference Best Paper Award, Intel Design and Test Technology Conference Best Paper Award, IBM Faculty Awards,Terman Fellowship, and the Intel Achievement Award, Intel’s highest corporate honor. At Stanford, he was honored multiple times by graduating seniors "for being important to them during their time at Stanford." Prof. Mitra also serves as an invited member on DARPA’s Information Science and Technology Board.