Deep Learning with Low Precision Hardware - Challenges and Opportunities for Logic Synthesis

Professor
Integrated Systems Laboratory
Digital Circuits and Systems Group
ETHZ, Zurich, Switzerland

 

Webpage

Friday, 29 September 2017 at 9:20 in room BC 420

 

Abstract:

Deep learning  has taken the world of cloud services by storm in just  a couple of years. Now we are bracing for the next wave of embedded  deep learning applications. In this context, however, power is tightly bound and general-purpose floating-point (FP) computations for inference and learning are too power hungry, and researchers in industry and academia are rushing to find robust and accurate solutions for deep learning on low-precision hardware.  In this talk I will survey recent progress in this very rapidly evolving area and highlight opportunities for  logic synthesis engines to provide differentiating value by enabling computer-aided optimal approximations and limited quality degradation, or even quality improvements, with respect to standard FP-based arithmetic circuits.
 

About the speaker:

Luca Benini is the chair of Digital Circuits and Systems at ETHZ. He has served as Chief Architect for the Platform2012/STHORM project in STmicroelectronics, Grenoble in the period 2009-2013. He has held visiting and consulting researcher positions at EPFL, IMEC, Hewlett-Packard Laboratories, Stanford University. He is also a Professor at University of Bologna, Italy.

Dr. Benini's research interests are in energy-efficient system design and Multi-Core SoC design. He is also active in the area of energy-efficient smart sensors and sensor networks for biomedical and ambient intelligence applications. In these areas he has coordinated tens of funded projects, including an on-going ERC Advanced Grant on Multi-scale thermal management of Computing Systems.

He has published more than 700 papers in peer-reviewed international journals and conferences, four books and several book chapters (h-index=82 on Google Scholar). He has been General Chair of the IEEE/ACM Symposium on Low Power Electronics, Network on Chip Symposium and Design and Test in Europe Conference. He is associate editor of the IEEE Transactions on Computer-Aided Design and of the ACM Transactions on Embedded Computing Systems. He is a Fellow of the IEEE and a member of the Academia Europaea and has served for two terms as a member of the steering board of the ARTEMISIA European Association on Advanced Research & Technology for Embedded Intelligence and Systems.