Computer-aided synthesis of digital circuits from behavioral level specifications offers an effective means to deal with the increasing complexity of digital hardware design. High-level Synthesis of ASICs under Timing and Synchronization Constraints addresses bot theoretical and practical aspects in the design of a high-level synthesis system that transforms a behavioral level description of hardware to a synchronous logic level implementation consisting of logic gates and registers.
High-level Synthesis of ASICs under Timing and Synchronization Constraints addresses specific issues in applying high-level synthesis techniques to the design of ASICs. This complements previous results achieved in synthesis of general-purpose and signal processors, where data-path design is of utmost importance. In contrast, ASIC designs are often characterized by complex control schemes, to support communication and synchronization with the environment. The combined design of efficient data path and control unit is the major contribution of this book.
The book can be ordered by calling Kluwer Academic Publishers at: + 617 871-6300. ISBN 0-7923-9244-2.