- L. Benini and G. De Micheli,
*Networks on Chips: A New SoC Paradigm*, IEEE Computers, January 2002, pp. 70-78. - G. De Micheli,
*Synthesis and optimization of digital circuits*, McGraw Hill, 1994.## Over 500 citations

- L. Benini, A. Bogliolo and G. De Micheli,
*A Survey of Design Techniques for System-Level Dynamic Power Management*, IEEE Transactions on VSLI, pp. 299-316, June 2000. - R. Gupta and G. De Micheli,
*Hardware /Software Co-synthesis for Digital Systems,*IEEE Design and Test, Vol. 10, No. 3, pp. 29-41, September 1993.## Over 200 citations

- L. Benini and G. De Micheli,
*System-Level Power Optimization: Techniques and Tools,*TODAES, ACM Transactions on Design Automation of Electronic Systems, Vol. 5, No. 2, pp. 115-192, April 2000. - L. Benini and G. De Micheli,
*Dynamic Power Management: design techniques and CAD tools*, Kluwer, 1998. - S. Murali and G. De Micheli,
*Bandwidth-Constrained Mapping of Cores onto NoC Architectures,*DATE, International Conference on Design and Test Europe, 2004, pp. 896-901. - D. Bertozzi, A. Jalabert, S. Murali, R. Tamhankar, S. Stergiou, L. Benini, and G. De Micheli,
*NoC Synthesis Flow for Customized Domain Specific Mutliprocessor Systems-on-Chip,*IEEE Transactions on Parallel and Distributed Systems, vol. 16, no. 2, pp. 113-129, 2005. - L. Benini, A. Bogliolo, G. Paleologo and G. De Micheli,
*Policy Optimization for Dynamic Power Management,*IEEE Transactions on CAD, Vol. 18, No. 6, June 1999, pp. 813-833. - L. Benini, G. De Micheli, E. Macii, D, Scuito and C. Silvano,
*Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems**,*Proceedings of the Great lakes Symposium on VSLI, March 1997, pp. 77-82. - T. Ye and G. De Micheli,
*Analysis of Power Consumption on Switch Fabrics in Network Routers,*DAC-Proceedings of the Design Automation Conference, 2002, pp. 524-530. - G. De Micheli, R. Brayton and A. Sangiovanni-Vincentelli,
*Optimal State Assignment for Finite State Machines,*IEEE Transactions on CAD/ICAS, Vol. CAD-4, No. 3, pp. 269-284, July 1985 and IBM Research Report, No. RC 10599. - A. Jalabert, S. Murali, L. Benini and G.De Micheli,
*XpipesCompiler: A Tool for instantiating Application-Specific Networks on Chips*, DATE, International Conference on Design and Test Europe, 2004, pp. 884-889. - T. Simunic, L. Benini, P. Glynn and G. De Micheli,
*Dynamic Power Management for Portable Systems,*MOBICOM, Proceeding of the International Conference on Mobile Computing and Networking, August 2000, pp. 11-19 - S. Murali and G. De Micheli,
*SUNMAP: A Tool for Automatic Toplogy Selection and Generation for NoCs,*DAC, Design Automation Conference, 2004, pp. 914-919. - T. Simunic, L. Benini, P. Glynn, G. De Micheli,
*Event-driven Power Management*, IEEE Transactions on CAD/ICAS, Vol. 20, No. 7, pp. 840-857, July 2001. - T. Simunic, L. Benini and G. De Micheli,
*Cycle-Accurate Simulation of energy Consumption in Embedded Systems,*DAC-Proceedings of the design Automation Conference, 1999, pp. 867-872.## Over 100 citations

- R. Gupta and G. De Micheli,
*System-level Synthesis Using Re-programmable Components,*EDAC, Proceedings of the European Design Automation Conference, Brussels, March 1992, pp. 2-7. - R. Gupta, C. Coelho and G. De Micheli,
*Synthesis and Simulation of Digital Systems Containing Interacting Hardware and Software Components,*DAC, Proceedings of the Design Automation Conference, Anaheim,June 1992, pp. 225-230. - T. Simunic, L. Benini, A. Acquaviva, P. Glynn and G. De Micheli,
*Dynamic Voltage Scaling and Power management for Portable Systems,*DAC-Proceedings of the Design Automation Conference, June 2001, pp. 524-529. - D. Ku and G. De Micheli,
*High-level Synthesis of ASICS under Timing and Synchronization Constraints*, Kluwer, 1992. - E.Y. Chung, L. Benini and G. De Micheli,
*Dynamic Power Management Using Adaptive Learning Tree,*ICCAD, Proceedings of the International Conference on Computer Aided Design, San Jose, CA, November 1999, pp. 274-279. - G. De Micheli and L. Benini,
*Networks on Chips*, Morgan Kaufmann, 2006. - G. De Micheli, D. Ku, F. Mailhot and T. Truong,
*The Olympus Synthesis System for Digital Design,*IEEE Design and Test, pp. 37-53, October 1990. - T. Simunic, L.Benini and G. De Micheli,
*Energy-Efficient Design of Battery-Powered Systems*, IEEE Transactions on VLSI, Vol. 9, No. 1, pp. 15-28, February 2001. - D. Bertozzi, L. Benini and G. De Micheli,
*Low Power Error-Resilient Encoding for On-Chip Data Buses,*DATE-International Conference on Design and Test in Europe, Paris, 2002, pp. 102-109 - P. Song and G. De Micheli,
*Circuit and Architecture Trade-Offs for High- Speed Multiplication,*IEEE Journal on Solid State Circuits, Vol. 26, No. 9, pp. 1184-1198, September 1991. - L. Benini and G. De Micheli,
*State Assignment for Low Power Dissipation,*IEEE Journal of Solid State Circuits, Vol. 30, No. 3, March 1995, pp. 258-268. - Y. H. Lu and G. De Micheli,
*Comparing System-Level Power Management Policies*, IEEE Design and Test, Vol. 18, No. 2, pp. 10-19, March-April 2001. - L. Benini, G. De Micheli, E. Macii, D. Scuito and C. Silvano,
*Address Bus Encoding Techniques for System-Level Power Optimization,*DATE, Proceedings of the Design Automation and Test in Europe Conference, 1998, pp. 861-866. - S. Murali, G. De Micheli, L. Benini, T. Theocharides, N. Vijaykrishnan, and M. Irwin,
*Analysis of Error Recovery Schemes for Networks on Chips,*Design & Test of Computers, vol. 22, no. 5, pp. 434-442, 2005. - Y. Lu, E.Y. Chung, T. Simunic, L. Benini and G. De Micheli,
*Quantitive Comparison of Power Management Algorithms**,*DATE, Proceedings of the Design Automation and Test in Europe, March 2000, pp. 20-26. - R. Gupta, C. Coelho and G. De Micheli,
*Program Implementation Schemes for Hardware-Software Systems,*IEEE Computer, Vol. 27, No. 1, January 1994, pp. 48-55 . - L. Benini and G. De Micheli,
*Automatic Synthesis of Low-Power Gated-Clock Finite-State Machines,*IEEE Transactions on CAD/ICAS, Vol. 15, No. 6, June 1996, pp. 630-643. - G. De Micheli,
*Synchronous Logic Synthesis: Algorithms for Cycle-Time Minimization**,*IEEE Transactions on CAD/ICAS, Vol. 10, No. 1, pp. 63-73, January 1991. - E. Y. Chung, L. Benini and G. De Micheli,
*Dynamic Power Management for Non-Stationary Service Requests,* - R. Brayton, R. Camposano, G. De Micheli, R. Otten and J. Van Eijndhoven,
*The Yorktown Silicon Compiler System,*in D. Gajski, Editor, "Silicon Compilation", pp. 204-310, Addison Wesley and IBM Report, No. RC 12500. - G. De Micheli, R.Ernst and W. Wolf,
*Readings in Hardware/Software Co-Design*, Morgan Kaufmann, 2003. - E.Y. Chung, L. Benini, A. Bogliolo, Y-H. Lu and G. De Micheli,
*Dynamic Power Management for Nonstationary Service Requests,*IEEE Transactions on Computer, Vol. 51, No. 11, November 2002, pp. 1345-1361 - L.Benini, E. Macii and G. De Micheli,
*Designing Low Power Circuits: Practical Recipes*, IEEE Circuit and System Magazine, Vol. 1, No. 1, First Quarter 2001, pp. 6-25. - Y. H. Lu and G. De Micheli,
*Adaptive Hard Disk Power Management on Personal Computers**,*Proceedings of the IEEE Great Lakes Symposium, 1999, pp. 50-53. - Y. Lu, L. Benini and G. De Micheli,
*Operating System Directed Power Reduction,*ISLPED, IEEE Symposium on Low Power Electronics and Design, 2000, pp. 37-42. - G. De Micheli and M. Sami,
*Hardware/Software Co-Design*, Kluwer, 1995.## Over 70 citations

- D. Wong, G. De Micheli and M. Flynn,
*Algorithms for Designing High-Performance Digital Circuits Using Wave Pipelining**,*IEEE Transactions on CAD/ICAS, Vol. 12, No. 5, January 1993, pp. 25-46. - G. De Micheli,
*Symbolic Design of Combinational and Sequential Circuits Implemented by Two-Level Logic Macros**,*IEEE Transactions on CAD/ICAS, October 1986, pp. 597-616 and IBM Research Report, No. RC 11672 and reprinted in A.R. Newton, Editor, Logic Synthesis for Integrated Circuit Design, IEEE Press, pp. 84-103, 1987 (IEEE/CAS 1986 CAD-Transactions Best Paper Award). - D. Ku and G. De Micheli,
*Hardware C: A Language for Hardware Description (Version 2.0),*CSL Report, TR-90-419, Stanford, 1990. - S. Murali, M. Coenen, A. Radulescu, K. Goossens, and G. De Micheli,
*A Methodology for Mapping Multiple Use-Cases onto Networks on Chips,*in Date06, pp. 118-123, 2006. - P. P. Pande, G. De Micheli, C. Grecu, A. Ivanov, and R. Saleh,
*Design, Synthesis, and Test of Network on Chips,*Design & Test of Computers, vol. 22, no. 5, pp. 404-413, 2005. - L. Benini and G. De Micheli,
*Transformation and Synthesis of FSMs for Low-Power Gated-Clock Implementation,*Proceedings of the International Symposium on Low Power Design, April 1995, pp. 21-26 (and reprinted in A. Chandrakasan and R. Brodersen, Low-Power CMOS Design, pp. 554-559. - G. De Micheli,
*Hardware Synthesis from C/C++ Models,*DATE, Proceedings of the Design Automation and test in Europe Conference, 1999, pp. 382-383. - R. Gupta and G. De Micheli,
*Partitioning of Functional Models of Synchronous Digital Systems**,*ICCAD, Proceedings of the International Conference on Computer Aided Design, Santa Clara, CA, November 1990, pp. 216-220. - L. Benini, P. Siegel and G. De Micheli,
*Saving Power by Synthesizing Gated Clocks for Sequential Circuits**,*IEEE Design and Test, Winter 1994, pp 32-41. - S. Murali, P. Meloni, F. Angiolini, D. Atienza, S. Carta, L. Benini, G. De Micheli, and L. Raffo,
*Designing Application-Specific Networks on Chips with Floorplan Information,*in Proceedings of the 2006 International Conference on Computer-Aided Design, pp. 355-362, 2006. - F. Worm, P. Thiran, P. Ienne and G. De Micheli,
*An Adaptive Low-power Transmission Scheme for On-chip Networks,*ISSS, International Symposium on Systems Synthesis, Kyoto, Japan, October 2002, pp. 92-100. - F. Mailhot and G. De Micheli,
*Technology Mapping with Boolean Matching and Don't Care Sets ,*European Design Automation Conference, Glasgow, Scotland, March 1990, pp. 212-216. - D. Bertozzi, L. Benini, and G. De Micheli,
*Error Control Schemes for On-chip Communication Links: the energy-reliability trade-off,*IEEE Transactions on CAD, vol. 24, no. 6, pp. 818-831, 2005. - N. Genko, D. Atienza, G. De Micheli, J. Mendias, R. Hermida, and F. Catthoor,
*A Complete Network-On-Chip Emulation Framework,*in DATE, no. 1, pp. 246 - 251, 2005. - Y. Lu, L. Benini and G. De Micheli,
*Power Aware Operating Systems for Interacting Systems*, IEEE Transactions on VSLI, April 2002, pp.70-78. - G. De Micheli,
*Computer-Aided Hardware/Software Co-Design,*IEEE Micro, pp 11-16, August 1994. - L. Benini, G. De Micheli, E. Macii, M. Poncico and S. Quer,
*System-Level Power Optimization of Special Purpose Applications: The Beach Solution,*ISLPED, IEEE Symposium on Low Power Electronics and Design, 1997, pp. 24-29. - L. Benini and G. De Micheli,
*Networks on Chip: A New Paradigm for Systems on Chip Design,*DATE-International Conference on Design and Test in Europe, Paris 2002, pp. 418-419. - Y. H. Lu, T. Simunic and G. De Micheli,
*Software Controlled Power Management,*CODES, Proceeding of the IEEE Hardware/Software C-design Workshop, 1999, pp. 157-161. - T. Simunic, H. Vikalo, P. Glynn and G. De Micheli,
*Energy Efficient Design of Portable Wireless Systems,*ISLPED, IEEE Symposium on Low Power Electronics and Design, 2000, pp. 49-54. - S. Murali, L. Benini, and G. De Micheli,
*Mapping and Physical Planning of Networks-on-Chip Architectures with Quality-of-Service Guarantees,*in Proceedings of the ASP-DAC 2005, vol. 1, pp. 27-32, 2005. - Y. Lu, L. Benini and G. De Micheli,
*Low-Power Task Scheduling for Multiple Devices,*CODES, Proceedings of the IEEE Hardware/Software C-Design Workshop, 2000, pp. 39-43. - D. Filo, D. Ku, C. Coelho and G. De Micheli,
*Interface Optimization for Concurrent Systems Under Timing Constraints,*IEEE Transactions on VLSI, Vol. 1, No. 3, pp. 268-281, September 1993. - T. Simunic, L. Benini, G. De Micheli and M. Hans,
*Source Code Optimization and Profiling of Energy Consumption in Embedded Systems,*ISSS, Proceedings of the International Symposium on System Synthesis, September 2000, pp. 193-198. - G. De Micheli and D. Ku,
*Hercules, a System for High-Level Synthesis,*DAC, Proceedings of the Design Automation Conference, Anaheim, CA, June 1988, pp. 483-488. - T. Tao Ye, L. Benini, G. De Micheli,
*Packetized On-Chip Interconnect Communication Analysis for MPSoC,*Proceedings of Design Automation and Test in Europe, DATE, March 2003, pp. 344-349. - L. Semeria and G. De Micheli,
*SpC: Synthesis of Pointers in C, Application of Pointer Analysis to the Behavioral Synthesis from C,*ICCAD, Proceedings of the International Conference on Computer Aided Design, San Jose, CA, November 1998, pp. 340-346. - L. Benini, G. De Micheli, E. Macii, M. Poncini, and S. Quer,
*Power Optimization of Core-Based Systems by Address Bus Encoding**,*IEEE Transactions on VLSI, Vol. 6, No. 4, December 1998, pp. 554-562. - L. Benini and G. De Micheli,
*Powering Networks on Chips: Energy-Efficient and Reliable Interconnect Design for SoCs**,*ISSS, Proceedings of the International Symposium on System Synthesis, Montreal, October, 2001, pp. 33-38.## Over 50 citations

- L. Benini, A. Bogliolo, M. Favalli and G. De Micheli,
*Regression Models for Behavioral Power Estimation*, Integrated Computer Aided Engineering, Vol. 5, No. 2, 1998, pp. 95-106. - L. Benini and G. De Micheli,
*Networks on Chips: Energy-Efficient and Reliable Interconnect Design for SoCs**,*ISSS, Proceedings of the International Symposium on System Synthesis, Montreal, October, 2001, pp. 33-38. - L. Semeria, K. Sato and G. De Micheli,
*Synthesis of Hardware Models in C with Pointers and Complex Data Structures*, IEEE Transactions on VLSI, Vol.9, No. 6, pp.743-756, December 2001. - S. Murali, M. Coenen, A. Radulescu, K. Goossens, and G. De Micheli,
*Mapping and Configuration Methods for Multi-Use-Case Networks on Chips,*in ASPDAC, vol. 1, pp. 146-151, 2006. - P. Siegel, G. De Micheli and D. Dill,
*Automatic Technology Mapping for Generalized Fundamental-Mode Asynchronous Designs,*DAC-Proceedings of the Design Automation conference, Dallas, June 1993, pp. 61-67 and CSL Report CSL-TR-93-580 (DAC 93 Best Paper Award). - L. Benini and G. De Micheli,
*A Survey of Boolean Matching Techniques for Library Binding**,*TODAES. ACM Transactions on Design Automation of Electronic Systems, Vol. 2, No. 3, July 1997, pp. 193-226. - J. Smith and G. De Micheli,
*Automated Composition of Hardware Components**,*DAC-Proceedings of the Design Automation Conference, 1998, pp. 14-19. - S. Murali and G. De Micheli,
*An Application-Specific Design Methodology for STbus Crossbar Generation,*in DATE, pp. 1176-1181, 2005. - A. Peymandoust, L. Pozzi, P. Ienne, G. De Micheli,
*Automatic instruction set extension and utilization for embedded processors*, Proceedings, IEEE International Conference on Application-Specific Systems, Architectures and Processors, June 2003, pp. 103-114. - V. Bertacco, S. Minato, P. Verplaetse, L. Benini and G. De Micheli,
*Decision Diagrams and Pass-Transistor Logic Synthesis,*International Logic Synthesis Workshop, 1997, Tahoe City, CA. - R. Gupta and G. De Micheli,
*Hardware/Software Co-Design,*IEEE Proceedings, Vol. 85, No. 3, March 1997, pp. 349-365. - S. Ercolani and G. De Micheli,
*Technology Mapping for Electrically Programmable Gate Arrays,*Design Automation Conference, San Francisco, June 1991, pp. 234-239. - Y-H. Lu,L. Benini, G. De Micheli,
*Dynamic Frequency Scaling with Buffer Insertion for Mixed Workloads,*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, Issue 11, November 2002, pp. 1284-1305. - Y. Sasaki and G. De Micheli,
*Cross-talk Delay Analysis Using Relative Window Method,*IEEE International ASIC/SOC Conference 1999, pp. 9-13. - L. Benini, A. Bogliolo and G. De Micheli,
*Dynamic Power Management of Electronic Systems,*ICCAD, Proceedings of the International Conference on Computer Aided Design, San Jose, CA, November 1998, pp. 696-702. - V. Amoia, G. De Micheli and M. Santomauro,
*Computer Aided Formulation of Transition Rate Matrices via Kronecker Algebra,*IEEE Transactions on Reliability, pp. 123-132, June 1981. - P. Vuillod, L. Benini, A. Bogliolo and G. De Micheli,
*Clock Skew Optimization for Peak Current Reduction,*Digest of the International Symposium on Low Power Electronics and Design, Monterey, 1996, pp. 265-270. - M. Platzner and G. De Micheli,
*Acceleration of Satisfiability Algorithms by Reconfiqurable Hardware,*FPL '98, Proceedings International Workshop of Field Programmable Logic and Applications, published as R. Hartenstein and Andres, Editors, Lecture Notes in Computer Science, No. 1482, Springer, 1998, pp. 69-78. - L. Benini, E. Macii, M. Poncini and G. De Micheli,
*Telescopic Units: A New Paradigm for Performance Optimization of VSLI Designs,*IEEE Transactions on CAD/ICAS, Vol. 17, No. 3, March 1998, pp. 220-231. - M. Barocci, L. Benini, A. Bogliolo, B. Ricco and G. De Micheli,
*Look-up Table Power Macro-models for Behavioral Library Components**,*Proceedings Volta Memorial Conference, Como, pp*.*173-181. - M. Damiani and G. De Micheli,
*Don't Care Specifications in Combinational and Synchronous Logic Circuits**,*IEEE Transactions on CAD/ICAS, Vol. 12, No. 3, March 1993, pp. 365-388 and CSL Report, CSL-TR-92-531, 1992. - F. Worm, P. Ienne, P. Thiran, and G. De Micheli,
*A Robust Self-calibrating Transmission Scheme for On-Chip Networks,*IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 1, pp. 126-139, 2005. - S. Murali, A. Mutapcic, D. Atienza, R. Gupta, S. P. Boyd, and G. De Micheli,
*Temperature-Aware Processor Frequency Assignment for MPSoCs Using Convex Optimization,*in Internacional Conference on Hardware/Software Codesign and System Synthesis, vol. (CODES+ISSS), ISBN: 978-1-59593-824-4/07/0009, pp. 111-116, 2007. - Y. H. Lu, L. Benini and G. De Micheli,
*Requester-Aware Power Reduction,*ISSS, Proceeding of the International Symposium on System Synthesis, September 2000, pp. 18-23. - M. Coenen, S. Murali, A. Radulescu, K. Goossens, and G. De Micheli,
*A buffer-sizing Algorithm for Networks on Chip using TDMA and credit-based end-to-end Flow Control,*in Proceedings of the conference on Design, automation and test in Europe: Proceedings, no. ISBN:3-9810801-0-6, pp. 118 - 123, 2006. - E.Y. Chung, L. Benini, and G. De Micheli,
*Contents Provider Assisted Dynamic Voltage Scaling for Low Energy MultiMedia Applications,*ISPLED, IEEE Symposium on Low Power Electronics and Design, 2002, pp. 42-47.